Lines Matching refs:RFPGA0_XAB_RFPARAMETER
454 rtlphy->phyreg_def[RF90_PATH_A].rflssi_select = RFPGA0_XAB_RFPARAMETER; in _rtl92d_phy_init_bb_rf_register_definition()
455 rtlphy->phyreg_def[RF90_PATH_B].rflssi_select = RFPGA0_XAB_RFPARAMETER; in _rtl92d_phy_init_bb_rf_register_definition()
2904 ret_value = rtl_get_bbreg(hw, RFPGA0_XAB_RFPARAMETER, in rtl92d_phy_sw_chnl()
3400 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(0), 0x0); in rtl92d_update_bbrf_configuration()
3401 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(15), 0x0); in rtl92d_update_bbrf_configuration()
3403 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(16), 0x0); in rtl92d_update_bbrf_configuration()
3404 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(31), 0x0); in rtl92d_update_bbrf_configuration()
3428 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(15), 0); in rtl92d_update_bbrf_configuration()
3449 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, in rtl92d_update_bbrf_configuration()
3455 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(0), 0x1); in rtl92d_update_bbrf_configuration()
3456 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(15), 0x1); in rtl92d_update_bbrf_configuration()
3458 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(16), 0x1); in rtl92d_update_bbrf_configuration()
3459 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(31), 0x1); in rtl92d_update_bbrf_configuration()
3486 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(15), in rtl92d_update_bbrf_configuration()
3498 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, in rtl92d_update_bbrf_configuration()