Lines Matching refs:PWR_BASEADDR_MAC
69 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(7), 0}, \
72 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(2), 0}, \
75 PWR_BASEADDR_MAC , PWR_CMD_WRITE, (BIT(4)|BIT(3)), 0}, \
78 PWR_BASEADDR_MAC , PWR_CMD_POLLING, BIT(1), BIT(1)}, \
81 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(0), BIT(0)}, \
84 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(0), BIT(0)}, \
87 PWR_BASEADDR_MAC , PWR_CMD_POLLING, BIT(0), 0},
95 PWR_BASEADDR_MAC , PWR_CMD_WRITE, 0xFF, 0}, \
98 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(7), 0}, \
101 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(1), BIT(1)}, \
104 PWR_BASEADDR_MAC , PWR_CMD_POLLING, BIT(1), 0},
112 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(4) | BIT(3), (BIT(4) | BIT(3))},\
115 PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, \
119 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3) | BIT(4)},\
139 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(3) | BIT(4), 0},
147 PWR_BASEADDR_MAC , PWR_CMD_WRITE, 0xFF, 0x20}, \
150 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(2), BIT(2)}, \
153 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(0), 0}, \
156 PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, \
160 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(2), BIT(2)}, \
180 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(0), BIT(0)}, \
183 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(2), 0}, \
186 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(3) | BIT(4), 0},
194 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(0), 0}, \
197 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(7), BIT(7)},
205 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(7), 0},
213 PWR_BASEADDR_MAC , PWR_CMD_WRITE, 0xFF, 0xFF}, \
216 PWR_BASEADDR_MAC , PWR_CMD_WRITE, 0xFF, 0xFF}, \
219 PWR_BASEADDR_MAC , PWR_CMD_POLLING, 0xFF, 0}, \
222 PWR_BASEADDR_MAC , PWR_CMD_POLLING, 0xFF, 0}, \
225 PWR_BASEADDR_MAC , PWR_CMD_POLLING, 0xFF, 0}, \
228 PWR_BASEADDR_MAC , PWR_CMD_POLLING, 0xFF, 0}, \
231 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(0), 0}, \
234 PWR_BASEADDR_MAC , PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US}, \
237 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(1), 0}, \
240 PWR_BASEADDR_MAC , PWR_CMD_WRITE, 0xFF, 0x03}, \
243 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(1), 0}, \
246 PWR_BASEADDR_MAC , PWR_CMD_WRITE, 0xFF, 0x00}, \
249 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(5), BIT(5)},
260 PWR_BASEADDR_MAC , PWR_CMD_WRITE, 0xFF, 0x84}, \
263 PWR_BASEADDR_MAC , PWR_CMD_WRITE, 0xFF, 0x84}, \
266 PWR_BASEADDR_MAC , PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS}, \
269 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(4), 0}, \
272 PWR_BASEADDR_MAC , PWR_CMD_POLLING, BIT(7), 0}, \
275 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(1), BIT(1)}, \
278 PWR_BASEADDR_MAC , PWR_CMD_WRITE, 0xFF, 0xFF}, \
281 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(1) | BIT(0), BIT(1) | BIT(0)},\
284 PWR_BASEADDR_MAC , PWR_CMD_WRITE, 0xFF, 0}, \
287 PWR_BASEADDR_MAC , PWR_CMD_WRITE, 0xFF, 0xFF},