715 	rtlphy->phyreg_def[RF90_PATH_C].rfintfs = RFPGA0_XCD_RFINTERFACESW;  in _rtl92s_phy_init_register_definition()
721 	rtlphy->phyreg_def[RF90_PATH_C].rfintfi = RFPGA0_XCD_RFINTERFACERB;  in _rtl92s_phy_init_register_definition()
727 	rtlphy->phyreg_def[RF90_PATH_C].rfintfo = RFPGA0_XC_RFINTERFACEOE;  in _rtl92s_phy_init_register_definition()
733 	rtlphy->phyreg_def[RF90_PATH_C].rfintfe = RFPGA0_XC_RFINTERFACEOE;  in _rtl92s_phy_init_register_definition()
741 	rtlphy->phyreg_def[RF90_PATH_C].rf3wire_offset =  in _rtl92s_phy_init_register_definition()
749 	rtlphy->phyreg_def[RF90_PATH_C].rflssi_select = RFPGA0_XCD_RFPARAMETER;  in _rtl92s_phy_init_register_definition()
755 	rtlphy->phyreg_def[RF90_PATH_C].rftxgain_stage = RFPGA0_TXGAINSTAGE;  in _rtl92s_phy_init_register_definition()
761 	rtlphy->phyreg_def[RF90_PATH_C].rfhssi_para1 = RFPGA0_XC_HSSIPARAMETER1;  in _rtl92s_phy_init_register_definition()
767 	rtlphy->phyreg_def[RF90_PATH_C].rfhssi_para2 = RFPGA0_XC_HSSIPARAMETER2;  in _rtl92s_phy_init_register_definition()
773 	rtlphy->phyreg_def[RF90_PATH_C].rfsw_ctrl = RFPGA0_XCD_SWITCHCONTROL;  in _rtl92s_phy_init_register_definition()
779 	rtlphy->phyreg_def[RF90_PATH_C].rfagc_control1 = ROFDM0_XCAGCCORE1;  in _rtl92s_phy_init_register_definition()
785 	rtlphy->phyreg_def[RF90_PATH_C].rfagc_control2 = ROFDM0_XCAGCCORE2;  in _rtl92s_phy_init_register_definition()
791 	rtlphy->phyreg_def[RF90_PATH_C].rfrxiq_imbal = ROFDM0_XCRXIQIMBALANCE;  in _rtl92s_phy_init_register_definition()
797 	rtlphy->phyreg_def[RF90_PATH_C].rfrx_afe = ROFDM0_XCRXAFE;  in _rtl92s_phy_init_register_definition()
803 	rtlphy->phyreg_def[RF90_PATH_C].rftxiq_imbal = ROFDM0_XCTXIQIMBALANCE;  in _rtl92s_phy_init_register_definition()
809 	rtlphy->phyreg_def[RF90_PATH_C].rftx_afe = ROFDM0_XCTXAFE;  in _rtl92s_phy_init_register_definition()
815 	rtlphy->phyreg_def[RF90_PATH_C].rf_rb = RFPGA0_XC_LSSIREADBACK;  in _rtl92s_phy_init_register_definition()
1021 	case RF90_PATH_C:  in rtl92s_phy_config_rf()