Lines Matching refs:PWR_CMD_WRITE
68 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(2), 0},\
74 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), BIT(0)},\
77 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), 0},\
80 PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT(4)|BIT(3)), 0},\
83 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), BIT(0)},\
93 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0}, \
95 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), 0},\
97 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), BIT(1)}, \
106 PWR_BASEADDR_MAC, PWR_CMD_WRITE, \
112 PWR_CMD_WRITE, \
117 PWR_CMD_WRITE, BIT(3)|BIT(4), \
122 PWR_CMD_WRITE, BIT(0), BIT(0)}, \
134 PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT(0), 0},\
140 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3)|BIT(4), 0},
149 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3)|BIT(4), BIT(3)}, \
153 PWR_CMD_WRITE, BIT(2), BIT(2)}, \
157 PWR_CMD_WRITE, BIT(0), BIT(0)}, \
170 PWR_CMD_WRITE, BIT(0), 0}, \
178 PWR_CMD_WRITE, BIT(3)|BIT(4), 0},\
182 PWR_CMD_WRITE, 0xFF, 0},
189 PWR_CMD_WRITE, BIT(0), 0},/* 0x04[16] = 0*/\
192 PWR_CMD_WRITE, BIT(7), BIT(7)},/* 0x04[15] = 1*/
199 PWR_CMD_WRITE, BIT(7), 0},/* 0x04[15] = 0*/
207 PWR_CMD_WRITE, 0xFF, 0xFF},/*PCIe DMA stop*/ \
210 PWR_CMD_WRITE, 0xFF, 0x7F},/*Tx Pause*/ \
230 PWR_CMD_WRITE, BIT(0), 0},\
236 PWR_CMD_WRITE, BIT(1), 0},/*Whole BB is reset*/ \
239 PWR_CMD_WRITE, 0xFF, 0x3F},/*Reset MAC TRX*/ \
242 PWR_CMD_WRITE, BIT(1), 0},/*check if removed later*/ \
246 PWR_CMD_WRITE, BIT(5), BIT(5)},\
253 PWR_CMD_WRITE, 0xFF, 0x84}, /*SDIO RPWM*/\
256 PWR_CMD_WRITE, 0xFF, 0x84}, /*USB RPWM*/\
259 PWR_CMD_WRITE, 0xFF, 0x84}, /*PCIe RPWM*/\
266 PWR_CMD_WRITE, BIT(4), 0}, \
274 PWR_CMD_WRITE, BIT(6)|BIT(7), 0},\
278 PWR_CMD_WRITE, BIT(1), BIT(1)},\
282 PWR_CMD_WRITE, 0xFF, 0xFF},\
286 PWR_CMD_WRITE, BIT(1)|BIT(0), BIT(1)|BIT(0)},\
289 PWR_CMD_WRITE, 0xFF, 0}, /*. 0x522 = 0*/