1524 	u32 reg_eac, reg_e94, reg_e9c, tmp;  in _rtl8723be_phy_path_a_iqk()  local
1567 	reg_eac = rtl_get_bbreg(hw, 0xeac, MASKDWORD);  in _rtl8723be_phy_path_a_iqk()
1571 	if (!(reg_eac & BIT(28)) &&  in _rtl8723be_phy_path_a_iqk()
1583 	if (!(reg_eac & BIT(28)) &&  in _rtl8723be_phy_path_a_iqk()
1597 	u32 reg_eac, reg_e94, reg_e9c, reg_ea4, u32tmp, tmp;  in _rtl8723be_phy_path_a_rx_iqk()  local
1646 	reg_eac = rtl_get_bbreg(hw, RRX_POWER_AFTER_IQK_A_2, MASKDWORD);  in _rtl8723be_phy_path_a_rx_iqk()
1650 	if (!(reg_eac & BIT(28)) &&  in _rtl8723be_phy_path_a_rx_iqk()
1662 	if (!(reg_eac & BIT(28)) &&  in _rtl8723be_phy_path_a_rx_iqk()
1717 	reg_eac = rtl_get_bbreg(hw, RRX_POWER_AFTER_IQK_A_2, MASKDWORD);  in _rtl8723be_phy_path_a_rx_iqk()
1725 	tmp = (reg_eac & 0x03FF0000) >> 16;  in _rtl8723be_phy_path_a_rx_iqk()
1729 	if (!(reg_eac & BIT(27)) &&  in _rtl8723be_phy_path_a_rx_iqk()
1731 	    (((reg_eac & 0x03FF0000) >> 16) != 0x36))  in _rtl8723be_phy_path_a_rx_iqk()
1733 	else if (!(reg_eac & BIT(27)) &&  in _rtl8723be_phy_path_a_rx_iqk()
1744 	u32 reg_eac, reg_e94, reg_e9c, tmp;  in _rtl8723be_phy_path_b_iqk()  local
1787 	reg_eac = rtl_get_bbreg(hw, RRX_POWER_AFTER_IQK_A_2, MASKDWORD);  in _rtl8723be_phy_path_b_iqk()
1791 	if (!(reg_eac & BIT(28)) &&  in _rtl8723be_phy_path_b_iqk()
1803 	if (!(reg_eac & BIT(28)) &&  in _rtl8723be_phy_path_b_iqk()
1817 	u32 reg_e94, reg_e9c, reg_ea4, reg_eac, u32tmp, tmp;  in _rtl8723be_phy_path_b_rx_iqk()  local
1865 	reg_eac = rtl_get_bbreg(hw, RRX_POWER_AFTER_IQK_A_2, MASKDWORD);  in _rtl8723be_phy_path_b_rx_iqk()
1869 	if (!(reg_eac & BIT(28)) &&  in _rtl8723be_phy_path_b_rx_iqk()
1881 	if (!(reg_eac & BIT(28)) &&  in _rtl8723be_phy_path_b_rx_iqk()
1935 	reg_eac = rtl_get_bbreg(hw, RRX_POWER_AFTER_IQK_A_2, MASKDWORD);  in _rtl8723be_phy_path_b_rx_iqk()
1939 	tmp = (reg_eac & 0x03FF0000) >> 16;  in _rtl8723be_phy_path_b_rx_iqk()
1944 	if (!(reg_eac & BIT(27)) &&  in _rtl8723be_phy_path_b_rx_iqk()
1946 	    (((reg_eac & 0x03FF0000) >> 16) != 0x36))  in _rtl8723be_phy_path_b_rx_iqk()
1948 	else if (!(reg_eac & BIT(27)) &&  in _rtl8723be_phy_path_b_rx_iqk()
2330 	long reg_e94, reg_e9c, reg_ea4, reg_eac, reg_eb4, reg_ebc, reg_ec4;  in rtl8723be_phy_iq_calibrate()  local
2413 		reg_eac = result[i][3];  in rtl8723be_phy_iq_calibrate()
2425 		reg_eac = result[final_candidate][3];  in rtl8723be_phy_iq_calibrate()