Lines Matching defs:rtl_dm
1638 struct rtl_dm { struct
1640 long entry_min_undec_sm_pwdb;
1641 long undec_sm_cck;
1642 long undec_sm_pwdb; /*out dm */
1643 long entry_max_undec_sm_pwdb;
1644 s32 ofdm_pkt_cnt;
1645 bool dm_initialgain_enable;
1646 bool dynamic_txpower_enable;
1647 bool current_turbo_edca;
1648 bool is_any_nonbepkts; /*out dm */
1649 bool is_cur_rdlstate;
1650 bool txpower_trackinginit;
1651 bool disable_framebursting;
1652 bool cck_inch14;
1653 bool txpower_tracking;
1654 bool useramask;
1655 bool rfpath_rxenable[4];
1656 bool inform_fw_driverctrldm;
1657 bool current_mrc_switch;
1658 u8 txpowercount;
1659 u8 powerindex_backup[6];
1661 u8 thermalvalue_rxgain;
1662 u8 thermalvalue_iqk;
1663 u8 thermalvalue_lck;
1664 u8 thermalvalue;
1665 u8 last_dtp_lvl;
1666 u8 thermalvalue_avg[AVG_THERMAL_NUM];
1667 u8 thermalvalue_avg_index;
1668 bool done_txpower;
1669 u8 dynamic_txhighpower_lvl; /*Tx high power level */
1670 u8 dm_flag; /*Indicate each dynamic mechanism's status. */
1671 u8 dm_flag_tmp;
1672 u8 dm_type;
1673 u8 dm_rssi_sel;
1674 u8 txpower_track_control;
1675 bool interrupt_migration;
1676 bool disable_tx_int;
1677 char ofdm_index[MAX_RF_PATH];
1678 u8 default_ofdm_index;
1679 u8 default_cck_index;
1680 char cck_index;
1681 char delta_power_index[MAX_RF_PATH];
1682 char delta_power_index_last[MAX_RF_PATH];
1683 char power_index_offset[MAX_RF_PATH];
1684 char absolute_ofdm_swing_idx[MAX_RF_PATH];
1685 char remnant_ofdm_swing_idx[MAX_RF_PATH];
1686 char remnant_cck_idx;
1687 bool modify_txagc_flag_path_a;
1688 bool modify_txagc_flag_path_b;
1690 bool one_entry_only;
1691 struct dm_phy_dbg_info dbginfo;
1694 bool atc_status;
1695 bool large_cfo_hit;
1696 bool is_freeze;
1697 int cfo_tail[2];
1698 int cfo_ave_pre;
1699 int crystal_cap;
1700 u8 cfo_threshold;
1701 u32 packet_count;
1702 u32 packet_count_pre;
1703 u8 tx_rate;
1706 u8 swing_idx_ofdm[MAX_RF_PATH];
1707 u8 swing_idx_ofdm_cur;
1708 u8 swing_idx_ofdm_base[MAX_RF_PATH];
1709 bool swing_flag_ofdm;
1710 u8 swing_idx_cck;
1711 u8 swing_idx_cck_cur;
1712 u8 swing_idx_cck_base;
1713 bool swing_flag_cck;
1715 char swing_diff_2g;
1716 char swing_diff_5g;
1718 u8 delta_swing_table_idx_24gccka_p[DEL_SW_IDX_SZ];
1719 u8 delta_swing_table_idx_24gccka_n[DEL_SW_IDX_SZ];
1720 u8 delta_swing_table_idx_24gcckb_p[DEL_SW_IDX_SZ];
1721 u8 delta_swing_table_idx_24gcckb_n[DEL_SW_IDX_SZ];
1722 u8 delta_swing_table_idx_24ga_p[DEL_SW_IDX_SZ];
1723 u8 delta_swing_table_idx_24ga_n[DEL_SW_IDX_SZ];
1724 u8 delta_swing_table_idx_24gb_p[DEL_SW_IDX_SZ];
1725 u8 delta_swing_table_idx_24gb_n[DEL_SW_IDX_SZ];
1726 u8 delta_swing_table_idx_5ga_p[BAND_NUM][DEL_SW_IDX_SZ];
1727 u8 delta_swing_table_idx_5ga_n[BAND_NUM][DEL_SW_IDX_SZ];
1728 u8 delta_swing_table_idx_5gb_p[BAND_NUM][DEL_SW_IDX_SZ];
1729 u8 delta_swing_table_idx_5gb_n[BAND_NUM][DEL_SW_IDX_SZ];
1730 u8 delta_swing_table_idx_24ga_p_8188e[DEL_SW_IDX_SZ];
1731 u8 delta_swing_table_idx_24ga_n_8188e[DEL_SW_IDX_SZ];
1734 bool supp_phymode_switch;
1737 struct fast_ant_training fat_table;
1739 u8 resp_tx_path;
1740 u8 path_sel;
1741 u32 patha_sum;
1742 u32 pathb_sum;
1743 u32 patha_cnt;
1744 u32 pathb_cnt;
1746 u8 pre_channel;
1747 u8 *p_channel;
1748 u8 linked_interval;
1750 u64 last_tx_ok_cnt;
1751 u64 last_rx_ok_cnt;
2839 #define rtl_dm(rtlpriv) (&((rtlpriv)->dm)) macro