Lines Matching refs:wl
660 static int wl18xx_identify_chip(struct wl1271 *wl) in wl18xx_identify_chip() argument
664 switch (wl->chip.id) { in wl18xx_identify_chip()
667 wl->chip.id); in wl18xx_identify_chip()
668 wl->sr_fw_name = WL18XX_FW_NAME; in wl18xx_identify_chip()
670 wl->plt_fw_name = WL18XX_FW_NAME; in wl18xx_identify_chip()
671 wl->quirks |= WLCORE_QUIRK_RX_BLOCKSIZE_ALIGN | in wl18xx_identify_chip()
678 wlcore_set_min_fw_ver(wl, WL18XX_CHIP_VER, in wl18xx_identify_chip()
686 wl->chip.id); in wl18xx_identify_chip()
691 wl1271_warning("unsupported chip id: 0x%x", wl->chip.id); in wl18xx_identify_chip()
696 wl->fw_mem_block_size = 272; in wl18xx_identify_chip()
697 wl->fwlog_end = 0x40000000; in wl18xx_identify_chip()
699 wl->scan_templ_id_2_4 = CMD_TEMPL_CFG_PROBE_REQ_2_4; in wl18xx_identify_chip()
700 wl->scan_templ_id_5 = CMD_TEMPL_CFG_PROBE_REQ_5; in wl18xx_identify_chip()
701 wl->sched_scan_templ_id_2_4 = CMD_TEMPL_PROBE_REQ_2_4_PERIODIC; in wl18xx_identify_chip()
702 wl->sched_scan_templ_id_5 = CMD_TEMPL_PROBE_REQ_5_PERIODIC; in wl18xx_identify_chip()
703 wl->max_channels_5 = WL18XX_MAX_CHANNELS_5GHZ; in wl18xx_identify_chip()
704 wl->ba_rx_session_count_max = WL18XX_RX_BA_MAX_SESSIONS; in wl18xx_identify_chip()
709 static int wl18xx_set_clk(struct wl1271 *wl) in wl18xx_set_clk() argument
714 ret = wlcore_set_partition(wl, &wl->ptable[PART_TOP_PRCM_ELP_SOC]); in wl18xx_set_clk()
720 ret = wl18xx_top_reg_read(wl, PRIMARY_CLK_DETECT, &clk_freq); in wl18xx_set_clk()
730 ret = wl18xx_top_reg_write(wl, PLLSH_COEX_PLL_N, in wl18xx_set_clk()
735 ret = wl18xx_top_reg_write(wl, PLLSH_COEX_PLL_M, in wl18xx_set_clk()
741 ret = wl18xx_top_reg_write(wl, PLLSH_COEX_PLL_SWALLOW_EN, in wl18xx_set_clk()
746 ret = wl18xx_top_reg_write(wl, PLLSH_WCS_PLL_N, in wl18xx_set_clk()
751 ret = wl18xx_top_reg_write(wl, PLLSH_WCS_PLL_M, in wl18xx_set_clk()
758 ret = wl18xx_top_reg_write(wl, PLLSH_WCS_PLL_Q_FACTOR_CFG_1, in wl18xx_set_clk()
765 ret = wl18xx_top_reg_write(wl, PLLSH_WCS_PLL_Q_FACTOR_CFG_2, in wl18xx_set_clk()
772 ret = wl18xx_top_reg_write(wl, PLLSH_WCS_PLL_P_FACTOR_CFG_1, in wl18xx_set_clk()
779 ret = wl18xx_top_reg_write(wl, PLLSH_WCS_PLL_P_FACTOR_CFG_2, in wl18xx_set_clk()
783 ret = wl18xx_top_reg_write(wl, PLLSH_WCS_PLL_SWALLOW_EN, in wl18xx_set_clk()
788 ret = wl18xx_top_reg_write(wl, PLLSH_WL_PLL_SEL, in wl18xx_set_clk()
794 ret = wl18xx_top_reg_write(wl, PLLSH_WL_PLL_EN, PLLSH_WL_PLL_EN_VAL1); in wl18xx_set_clk()
801 ret = wl18xx_top_reg_write(wl, PLLSH_WL_PLL_EN, PLLSH_WL_PLL_EN_VAL2); in wl18xx_set_clk()
806 ret = wl18xx_top_reg_write(wl, PLLSH_COEX_PLL_SWALLOW_EN, in wl18xx_set_clk()
815 static int wl18xx_boot_soft_reset(struct wl1271 *wl) in wl18xx_boot_soft_reset() argument
820 ret = wlcore_write32(wl, WL18XX_ENABLE, 0x0); in wl18xx_boot_soft_reset()
825 ret = wlcore_write32(wl, WL18XX_SPARE_A2, 0xffff); in wl18xx_boot_soft_reset()
831 static int wl18xx_pre_boot(struct wl1271 *wl) in wl18xx_pre_boot() argument
835 ret = wl18xx_set_clk(wl); in wl18xx_pre_boot()
840 ret = wlcore_write32(wl, WL18XX_WELP_ARM_COMMAND, WELP_ARM_COMMAND_VAL); in wl18xx_pre_boot()
846 ret = wlcore_set_partition(wl, &wl->ptable[PART_BOOT]); in wl18xx_pre_boot()
851 ret = wlcore_write_reg(wl, REG_INTERRUPT_MASK, WL1271_ACX_INTR_ALL); in wl18xx_pre_boot()
855 ret = wl18xx_boot_soft_reset(wl); in wl18xx_pre_boot()
861 static int wl18xx_pre_upload(struct wl1271 *wl) in wl18xx_pre_upload() argument
869 ret = wlcore_set_partition(wl, &wl->ptable[PART_BOOT]); in wl18xx_pre_upload()
874 ret = wlcore_write32(wl, WL18XX_EEPROMLESS_IND, WL18XX_EEPROMLESS_IND); in wl18xx_pre_upload()
878 ret = wlcore_read_reg(wl, REG_CHIP_ID_B, &tmp); in wl18xx_pre_upload()
884 ret = wlcore_read32(wl, WL18XX_SCR_PAD2, &tmp); in wl18xx_pre_upload()
895 ret = wlcore_set_partition(wl, &wl->ptable[PART_PHY_INIT]); in wl18xx_pre_upload()
900 ret = wlcore_write32(wl, WL18XX_PHY_FPGA_SPARE_1, in wl18xx_pre_upload()
906 ret = wlcore_write32(wl, WL18XX_PHY_FPGA_SPARE_1, in wl18xx_pre_upload()
912 ret = wlcore_write32(wl, WL18XX_PHY_FPGA_SPARE_1, in wl18xx_pre_upload()
919 static int wl18xx_set_mac_and_phy(struct wl1271 *wl) in wl18xx_set_mac_and_phy() argument
921 struct wl18xx_priv *priv = wl->priv; in wl18xx_set_mac_and_phy()
931 ret = wlcore_set_partition(wl, &wl->ptable[PART_PHY_INIT]); in wl18xx_set_mac_and_phy()
935 ret = wlcore_write(wl, WL18XX_PHY_INIT_MEM_ADDR, params, in wl18xx_set_mac_and_phy()
943 static int wl18xx_enable_interrupts(struct wl1271 *wl) in wl18xx_enable_interrupts() argument
951 ret = wlcore_write_reg(wl, REG_INTERRUPT_MASK, event_mask); in wl18xx_enable_interrupts()
955 wlcore_enable_interrupts(wl); in wl18xx_enable_interrupts()
957 ret = wlcore_write_reg(wl, REG_INTERRUPT_MASK, in wl18xx_enable_interrupts()
965 wlcore_disable_interrupts(wl); in wl18xx_enable_interrupts()
971 static int wl18xx_boot(struct wl1271 *wl) in wl18xx_boot() argument
975 ret = wl18xx_pre_boot(wl); in wl18xx_boot()
979 ret = wl18xx_pre_upload(wl); in wl18xx_boot()
983 ret = wlcore_boot_upload_firmware(wl); in wl18xx_boot()
987 ret = wl18xx_set_mac_and_phy(wl); in wl18xx_boot()
991 wl->event_mask = BSS_LOSS_EVENT_ID | in wl18xx_boot()
1008 wl->ap_event_mask = MAX_TX_FAILURE_EVENT_ID; in wl18xx_boot()
1010 ret = wlcore_boot_run_firmware(wl); in wl18xx_boot()
1014 ret = wl18xx_enable_interrupts(wl); in wl18xx_boot()
1020 static int wl18xx_trigger_cmd(struct wl1271 *wl, int cmd_box_addr, in wl18xx_trigger_cmd() argument
1023 struct wl18xx_priv *priv = wl->priv; in wl18xx_trigger_cmd()
1028 return wlcore_write(wl, cmd_box_addr, priv->cmd_buf, in wl18xx_trigger_cmd()
1032 static int wl18xx_ack_event(struct wl1271 *wl) in wl18xx_ack_event() argument
1034 return wlcore_write_reg(wl, REG_INTERRUPT_TRIG, in wl18xx_ack_event()
1038 static u32 wl18xx_calc_tx_blocks(struct wl1271 *wl, u32 len, u32 spare_blks) in wl18xx_calc_tx_blocks() argument
1045 wl18xx_set_tx_desc_blocks(struct wl1271 *wl, struct wl1271_tx_hw_descr *desc, in wl18xx_set_tx_desc_blocks() argument
1052 wl18xx_set_tx_desc_data_len(struct wl1271 *wl, struct wl1271_tx_hw_descr *desc, in wl18xx_set_tx_desc_data_len() argument
1058 if (wl->quirks & WLCORE_QUIRK_TX_PAD_LAST_FRAME) in wl18xx_set_tx_desc_data_len()
1071 wl18xx_get_rx_buf_align(struct wl1271 *wl, u32 rx_desc) in wl18xx_get_rx_buf_align() argument
1079 static u32 wl18xx_get_rx_packet_len(struct wl1271 *wl, void *rx_data, in wl18xx_get_rx_packet_len() argument
1091 static void wl18xx_tx_immediate_completion(struct wl1271 *wl) in wl18xx_tx_immediate_completion() argument
1093 wl18xx_tx_immediate_complete(wl); in wl18xx_tx_immediate_completion()
1096 static int wl18xx_set_host_cfg_bitmap(struct wl1271 *wl, u32 extra_mem_blk) in wl18xx_set_host_cfg_bitmap() argument
1104 if (wl->quirks & WLCORE_QUIRK_TX_BLOCKSIZE_ALIGN) { in wl18xx_set_host_cfg_bitmap()
1110 if (wl->quirks & WLCORE_QUIRK_RX_BLOCKSIZE_ALIGN) { in wl18xx_set_host_cfg_bitmap()
1115 ret = wl18xx_acx_host_if_cfg_bitmap(wl, host_cfg_bitmap, in wl18xx_set_host_cfg_bitmap()
1124 static int wl18xx_hw_init(struct wl1271 *wl) in wl18xx_hw_init() argument
1127 struct wl18xx_priv *priv = wl->priv; in wl18xx_hw_init()
1134 ret = wl18xx_set_host_cfg_bitmap(wl, WL18XX_TX_HW_BLOCK_SPARE); in wl18xx_hw_init()
1139 ret = wl18xx_acx_set_checksum_state(wl); in wl18xx_hw_init()
1147 static void wl18xx_convert_fw_status(struct wl1271 *wl, void *raw_fw_status, in wl18xx_convert_fw_status() argument
1180 static void wl18xx_set_tx_desc_csum(struct wl1271 *wl, in wl18xx_set_tx_desc_csum() argument
1210 static void wl18xx_set_rx_csum(struct wl1271 *wl, in wl18xx_set_rx_csum() argument
1218 static bool wl18xx_is_mimo_supported(struct wl1271 *wl) in wl18xx_is_mimo_supported() argument
1220 struct wl18xx_priv *priv = wl->priv; in wl18xx_is_mimo_supported()
1234 static u32 wl18xx_sta_get_ap_rate_mask(struct wl1271 *wl, in wl18xx_sta_get_ap_rate_mask() argument
1246 } else if (wl18xx_is_mimo_supported(wl)) { in wl18xx_sta_get_ap_rate_mask()
1254 static u32 wl18xx_ap_get_mimo_wide_rate_mask(struct wl1271 *wl, in wl18xx_ap_get_mimo_wide_rate_mask() argument
1266 } else if (wl18xx_is_mimo_supported(wl) && in wl18xx_ap_get_mimo_wide_rate_mask()
1305 static int wl18xx_get_pg_ver(struct wl1271 *wl, s8 *ver) in wl18xx_get_pg_ver() argument
1311 ret = wlcore_set_partition(wl, &wl->ptable[PART_TOP_PRCM_ELP_SOC]); in wl18xx_get_pg_ver()
1315 ret = wlcore_read32(wl, WL18XX_REG_FUSE_DATA_2_3, &fuse); in wl18xx_get_pg_ver()
1321 ret = wlcore_read32(wl, WL18XX_REG_FUSE_DATA_1_3, &fuse); in wl18xx_get_pg_ver()
1335 ret = wlcore_read32(wl, WL18XX_REG_FUSE_DATA_2_3, &fuse); in wl18xx_get_pg_ver()
1347 ret = wlcore_set_partition(wl, &wl->ptable[PART_BOOT]); in wl18xx_get_pg_ver()
1354 static int wl18xx_conf_init(struct wl1271 *wl, struct device *dev) in wl18xx_conf_init() argument
1356 struct wl18xx_priv *priv = wl->priv; in wl18xx_conf_init()
1393 memcpy(&wl->conf, &conf_file->core, sizeof(wl18xx_conf)); in wl18xx_conf_init()
1402 memcpy(&wl->conf, &wl18xx_conf, sizeof(wl18xx_conf)); in wl18xx_conf_init()
1414 static int wl18xx_plt_init(struct wl1271 *wl) in wl18xx_plt_init() argument
1419 if (wl->plt_mode == PLT_FEM_DETECT) { in wl18xx_plt_init()
1424 ret = wlcore_write32(wl, WL18XX_SCR_PAD8, WL18XX_SCR_PAD8_PLT); in wl18xx_plt_init()
1428 return wl->ops->boot(wl); in wl18xx_plt_init()
1431 static int wl18xx_get_mac(struct wl1271 *wl) in wl18xx_get_mac() argument
1436 ret = wlcore_set_partition(wl, &wl->ptable[PART_TOP_PRCM_ELP_SOC]); in wl18xx_get_mac()
1440 ret = wlcore_read32(wl, WL18XX_REG_FUSE_BD_ADDR_1, &mac1); in wl18xx_get_mac()
1444 ret = wlcore_read32(wl, WL18XX_REG_FUSE_BD_ADDR_2, &mac2); in wl18xx_get_mac()
1449 wl->fuse_oui_addr = ((mac2 & 0xffff) << 8) + in wl18xx_get_mac()
1451 wl->fuse_nic_addr = (mac1 & 0xffffff); in wl18xx_get_mac()
1453 if (!wl->fuse_oui_addr && !wl->fuse_nic_addr) { in wl18xx_get_mac()
1458 wl->fuse_oui_addr = (mac[0] << 16) + (mac[1] << 8) + mac[2]; in wl18xx_get_mac()
1459 wl->fuse_nic_addr = (mac[3] << 16) + (mac[4] << 8) + mac[5]; in wl18xx_get_mac()
1463 ret = wlcore_set_partition(wl, &wl->ptable[PART_DOWN]); in wl18xx_get_mac()
1469 static int wl18xx_handle_static_data(struct wl1271 *wl, in wl18xx_handle_static_data() argument
1475 strncpy(wl->chip.phy_fw_ver_str, static_data_priv->phy_version, in wl18xx_handle_static_data()
1476 sizeof(wl->chip.phy_fw_ver_str)); in wl18xx_handle_static_data()
1479 wl->chip.phy_fw_ver_str[sizeof(wl->chip.phy_fw_ver_str) - 1] = '\0'; in wl18xx_handle_static_data()
1486 static int wl18xx_get_spare_blocks(struct wl1271 *wl, bool is_gem) in wl18xx_get_spare_blocks() argument
1488 struct wl18xx_priv *priv = wl->priv; in wl18xx_get_spare_blocks()
1497 static int wl18xx_set_key(struct wl1271 *wl, enum set_key_cmd cmd, in wl18xx_set_key() argument
1502 struct wl18xx_priv *priv = wl->priv; in wl18xx_set_key()
1512 ret = wlcore_set_key(wl, cmd, vif, sta, key_conf); in wl18xx_set_key()
1540 ret = wl18xx_set_host_cfg_bitmap(wl, in wl18xx_set_key()
1543 ret = wl18xx_set_host_cfg_bitmap(wl, in wl18xx_set_key()
1550 static u32 wl18xx_pre_pkt_send(struct wl1271 *wl, in wl18xx_pre_pkt_send() argument
1553 if (wl->quirks & WLCORE_QUIRK_TX_PAD_LAST_FRAME) { in wl18xx_pre_pkt_send()
1557 last_desc = (struct wl1271_tx_hw_descr *)(wl->aggr_buf + in wl18xx_pre_pkt_send()
1569 static void wl18xx_sta_rc_update(struct wl1271 *wl, in wl18xx_sta_rc_update() argument
1590 wl18xx_acx_peer_ht_operation_mode(wl, wlvif->sta.hlid, wide); in wl18xx_sta_rc_update()
1595 static int wl18xx_set_peer_cap(struct wl1271 *wl, in wl18xx_set_peer_cap() argument
1600 return wl18xx_acx_set_peer_cap(wl, ht_cap, allow_ht_operation, in wl18xx_set_peer_cap()
1604 static bool wl18xx_lnk_high_prio(struct wl1271 *wl, u8 hlid, in wl18xx_lnk_high_prio() argument
1609 (struct wl18xx_fw_status_priv *)wl->fw_status->priv; in wl18xx_lnk_high_prio()
1622 if (test_bit(hlid, &wl->fw_fast_lnk_map) && in wl18xx_lnk_high_prio()
1623 !test_bit(hlid, &wl->ap_fw_ps_map)) in wl18xx_lnk_high_prio()
1631 static bool wl18xx_lnk_low_prio(struct wl1271 *wl, u8 hlid, in wl18xx_lnk_low_prio() argument
1636 (struct wl18xx_fw_status_priv *)wl->fw_status->priv; in wl18xx_lnk_low_prio()
1646 else if (test_bit(hlid, &wl->fw_fast_lnk_map) && in wl18xx_lnk_low_prio()
1647 !test_bit(hlid, &wl->ap_fw_ps_map)) in wl18xx_lnk_low_prio()
1655 static u32 wl18xx_convert_hwaddr(struct wl1271 *wl, u32 hwaddr) in wl18xx_convert_hwaddr() argument
1660 static int wl18xx_setup(struct wl1271 *wl);
1809 static int wl18xx_setup(struct wl1271 *wl) in wl18xx_setup() argument
1811 struct wl18xx_priv *priv = wl->priv; in wl18xx_setup()
1817 wl->rtable = wl18xx_rtable; in wl18xx_setup()
1818 wl->num_tx_desc = WL18XX_NUM_TX_DESCRIPTORS; in wl18xx_setup()
1819 wl->num_rx_desc = WL18XX_NUM_RX_DESCRIPTORS; in wl18xx_setup()
1820 wl->num_links = WL18XX_MAX_LINKS; in wl18xx_setup()
1821 wl->max_ap_stations = WL18XX_MAX_AP_STATIONS; in wl18xx_setup()
1822 wl->iface_combinations = wl18xx_iface_combinations; in wl18xx_setup()
1823 wl->n_iface_combinations = ARRAY_SIZE(wl18xx_iface_combinations); in wl18xx_setup()
1824 wl->num_mac_addr = WL18XX_NUM_MAC_ADDRESSES; in wl18xx_setup()
1825 wl->band_rate_to_idx = wl18xx_band_rate_to_idx; in wl18xx_setup()
1826 wl->hw_tx_rate_tbl_size = WL18XX_CONF_HW_RXTX_RATE_MAX; in wl18xx_setup()
1827 wl->hw_min_ht_rate = WL18XX_CONF_HW_RXTX_RATE_MCS0; in wl18xx_setup()
1828 wl->fw_status_len = sizeof(struct wl18xx_fw_status); in wl18xx_setup()
1829 wl->fw_status_priv_len = sizeof(struct wl18xx_fw_status_priv); in wl18xx_setup()
1830 wl->stats.fw_stats_len = sizeof(struct wl18xx_acx_statistics); in wl18xx_setup()
1831 wl->static_data_priv_len = sizeof(struct wl18xx_static_data_priv); in wl18xx_setup()
1834 wl->num_rx_desc = num_rx_desc_param; in wl18xx_setup()
1836 ret = wl18xx_conf_init(wl, wl->dev); in wl18xx_setup()
1903 if (wl18xx_is_mimo_supported(wl)) in wl18xx_setup()
1904 wlcore_set_ht_cap(wl, IEEE80211_BAND_2GHZ, in wl18xx_setup()
1907 wlcore_set_ht_cap(wl, IEEE80211_BAND_2GHZ, in wl18xx_setup()
1911 wlcore_set_ht_cap(wl, IEEE80211_BAND_5GHZ, in wl18xx_setup()
1914 wlcore_set_ht_cap(wl, IEEE80211_BAND_2GHZ, in wl18xx_setup()
1916 wlcore_set_ht_cap(wl, IEEE80211_BAND_5GHZ, in wl18xx_setup()
1919 wlcore_set_ht_cap(wl, IEEE80211_BAND_2GHZ, in wl18xx_setup()
1921 wlcore_set_ht_cap(wl, IEEE80211_BAND_5GHZ, in wl18xx_setup()
1931 wl->enable_11a = (priv->conf.phy.number_of_assembled_ant5 != 0); in wl18xx_setup()
1938 struct wl1271 *wl; in wl18xx_probe() local
1951 wl = hw->priv; in wl18xx_probe()
1952 wl->ops = &wl18xx_ops; in wl18xx_probe()
1953 wl->ptable = wl18xx_ptable; in wl18xx_probe()
1954 ret = wlcore_probe(wl, pdev); in wl18xx_probe()
1961 wlcore_free_hw(wl); in wl18xx_probe()