135 static inline void mvebu_writel(struct mvebu_pcie_port *port, u32 val, u32 reg)  in mvebu_writel()  function
162 	mvebu_writel(port, stat, PCIE_STAT_OFF);  in mvebu_pcie_set_local_bus_nr()
172 	mvebu_writel(port, stat, PCIE_STAT_OFF);  in mvebu_pcie_set_local_dev_nr()
190 		mvebu_writel(port, 0, PCIE_BAR_CTRL_OFF(i));  in mvebu_pcie_setup_wins()
191 		mvebu_writel(port, 0, PCIE_BAR_LO_OFF(i));  in mvebu_pcie_setup_wins()
192 		mvebu_writel(port, 0, PCIE_BAR_HI_OFF(i));  in mvebu_pcie_setup_wins()
196 		mvebu_writel(port, 0, PCIE_WIN04_CTRL_OFF(i));  in mvebu_pcie_setup_wins()
197 		mvebu_writel(port, 0, PCIE_WIN04_BASE_OFF(i));  in mvebu_pcie_setup_wins()
198 		mvebu_writel(port, 0, PCIE_WIN04_REMAP_OFF(i));  in mvebu_pcie_setup_wins()
201 	mvebu_writel(port, 0, PCIE_WIN5_CTRL_OFF);  in mvebu_pcie_setup_wins()
202 	mvebu_writel(port, 0, PCIE_WIN5_BASE_OFF);  in mvebu_pcie_setup_wins()
203 	mvebu_writel(port, 0, PCIE_WIN5_REMAP_OFF);  in mvebu_pcie_setup_wins()
210 		mvebu_writel(port, cs->base & 0xffff0000,  in mvebu_pcie_setup_wins()
212 		mvebu_writel(port, 0, PCIE_WIN04_REMAP_OFF(i));  in mvebu_pcie_setup_wins()
213 		mvebu_writel(port,  in mvebu_pcie_setup_wins()
227 	mvebu_writel(port, dram->cs[0].base, PCIE_BAR_LO_OFF(1));  in mvebu_pcie_setup_wins()
228 	mvebu_writel(port, 0, PCIE_BAR_HI_OFF(1));  in mvebu_pcie_setup_wins()
229 	mvebu_writel(port, ((size - 1) & 0xffff0000) | 1,  in mvebu_pcie_setup_wins()
245 	mvebu_writel(port, cmd, PCIE_CMD_OFF);  in mvebu_pcie_setup_hw()
250 	mvebu_writel(port, mask, PCIE_MASK_OFF);  in mvebu_pcie_setup_hw()
257 	mvebu_writel(port, PCIE_CONF_ADDR(bus->number, devfn, where),  in mvebu_pcie_hw_rd_conf()
276 	mvebu_writel(port, PCIE_CONF_ADDR(bus->number, devfn, where),  in mvebu_pcie_hw_wr_conf()
289 	mvebu_writel(port, _val, PCIE_CONF_DATA_OFF);  in mvebu_pcie_hw_wr_conf()
925 		mvebu_writel(port, port->saved_pcie_stat, PCIE_STAT_OFF);  in mvebu_pcie_resume()