Lines Matching refs:dev
37 static void quirk_mmio_always_on(struct pci_dev *dev) in quirk_mmio_always_on() argument
39 dev->mmio_always_on = 1; in quirk_mmio_always_on()
48 static void quirk_mellanox_tavor(struct pci_dev *dev) in quirk_mellanox_tavor() argument
50 dev->broken_parity_status = 1; /* This device gives false positives */ in quirk_mellanox_tavor()
57 static void quirk_passive_release(struct pci_dev *dev) in quirk_passive_release() argument
67 dev_info(&d->dev, "PIIX3: Enabling Passive Release\n"); in quirk_passive_release()
83 static void quirk_isa_dma_hangs(struct pci_dev *dev) in quirk_isa_dma_hangs() argument
87 dev_info(&dev->dev, "Activating ISA DMA hang workarounds\n"); in quirk_isa_dma_hangs()
106 static void quirk_tigerpoint_bm_sts(struct pci_dev *dev) in quirk_tigerpoint_bm_sts() argument
111 pci_read_config_dword(dev, 0x40, &pmbase); in quirk_tigerpoint_bm_sts()
116 dev_info(&dev->dev, FW_BUG "TigerPoint LPC.BM_STS cleared\n"); in quirk_tigerpoint_bm_sts()
125 static void quirk_nopcipci(struct pci_dev *dev) in quirk_nopcipci() argument
128 dev_info(&dev->dev, "Disabling direct PCI/PCI transfers\n"); in quirk_nopcipci()
135 static void quirk_nopciamd(struct pci_dev *dev) in quirk_nopciamd() argument
138 pci_read_config_byte(dev, 0x08, &rev); in quirk_nopciamd()
141 dev_info(&dev->dev, "Chipset erratum: Disabling direct PCI/AGP transfers\n"); in quirk_nopciamd()
150 static void quirk_triton(struct pci_dev *dev) in quirk_triton() argument
153 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n"); in quirk_triton()
173 static void quirk_vialatency(struct pci_dev *dev) in quirk_vialatency() argument
208 pci_read_config_byte(dev, 0x76, &busarb); in quirk_vialatency()
213 pci_write_config_byte(dev, 0x76, busarb); in quirk_vialatency()
214 dev_info(&dev->dev, "Applying VIA southbridge workaround\n"); in quirk_vialatency()
229 static void quirk_viaetbf(struct pci_dev *dev) in quirk_viaetbf() argument
232 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n"); in quirk_viaetbf()
238 static void quirk_vsfx(struct pci_dev *dev) in quirk_vsfx() argument
241 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n"); in quirk_vsfx()
253 static void quirk_alimagik(struct pci_dev *dev) in quirk_alimagik() argument
256 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n"); in quirk_alimagik()
267 static void quirk_natoma(struct pci_dev *dev) in quirk_natoma() argument
270 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n"); in quirk_natoma()
285 static void quirk_citrine(struct pci_dev *dev) in quirk_citrine() argument
287 dev->cfg_size = 0xA0; in quirk_citrine()
292 static void quirk_extend_bar_to_page(struct pci_dev *dev) in quirk_extend_bar_to_page() argument
297 struct resource *r = &dev->resource[i]; in quirk_extend_bar_to_page()
303 dev_info(&dev->dev, "expanded BAR %d to page size: %pR\n", in quirk_extend_bar_to_page()
314 static void quirk_s3_64M(struct pci_dev *dev) in quirk_s3_64M() argument
316 struct resource *r = &dev->resource[0]; in quirk_s3_64M()
327 static void quirk_io(struct pci_dev *dev, int pos, unsigned size, in quirk_io() argument
332 struct resource *res = dev->resource + pos; in quirk_io()
334 pci_read_config_dword(dev, PCI_BASE_ADDRESS_0 + (pos << 2), ®ion); in quirk_io()
339 res->name = pci_name(dev); in quirk_io()
348 pcibios_bus_to_resource(dev->bus, res, &bus_region); in quirk_io()
350 dev_info(&dev->dev, FW_BUG "%s quirk: reg 0x%x: %pR\n", in quirk_io()
363 static void quirk_cs5536_vsa(struct pci_dev *dev) in quirk_cs5536_vsa() argument
367 if (pci_resource_len(dev, 0) != 8) { in quirk_cs5536_vsa()
368 quirk_io(dev, 0, 8, name); /* SMB */ in quirk_cs5536_vsa()
369 quirk_io(dev, 1, 256, name); /* GPIO */ in quirk_cs5536_vsa()
370 quirk_io(dev, 2, 64, name); /* MFGPT */ in quirk_cs5536_vsa()
371 dev_info(&dev->dev, "%s bug detected (incorrect header); workaround applied\n", in quirk_cs5536_vsa()
377 static void quirk_io_region(struct pci_dev *dev, int port, in quirk_io_region() argument
382 struct resource *res = dev->resource + nr; in quirk_io_region()
384 pci_read_config_word(dev, port, ®ion); in quirk_io_region()
390 res->name = pci_name(dev); in quirk_io_region()
396 pcibios_bus_to_resource(dev->bus, res, &bus_region); in quirk_io_region()
398 if (!pci_claim_resource(dev, nr)) in quirk_io_region()
399 dev_info(&dev->dev, "quirk: %pR claimed by %s\n", res, name); in quirk_io_region()
406 static void quirk_ati_exploding_mce(struct pci_dev *dev) in quirk_ati_exploding_mce() argument
408 dev_info(&dev->dev, "ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb\n"); in quirk_ati_exploding_mce()
446 static void quirk_ali7101_acpi(struct pci_dev *dev) in quirk_ali7101_acpi() argument
448 quirk_io_region(dev, 0xE0, 64, PCI_BRIDGE_RESOURCES, "ali7101 ACPI"); in quirk_ali7101_acpi()
449 quirk_io_region(dev, 0xE2, 32, PCI_BRIDGE_RESOURCES+1, "ali7101 SMB"); in quirk_ali7101_acpi()
453 static void piix4_io_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int e… in piix4_io_quirk() argument
458 pci_read_config_dword(dev, port, &devres); in piix4_io_quirk()
476 dev_info(&dev->dev, "%s PIO at %04x-%04x\n", name, base, in piix4_io_quirk()
480 static void piix4_mem_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int … in piix4_mem_quirk() argument
485 pci_read_config_dword(dev, port, &devres); in piix4_mem_quirk()
502 dev_info(&dev->dev, "%s MMIO at %04x-%04x\n", name, base, in piix4_mem_quirk()
512 static void quirk_piix4_acpi(struct pci_dev *dev) in quirk_piix4_acpi() argument
516 quirk_io_region(dev, 0x40, 64, PCI_BRIDGE_RESOURCES, "PIIX4 ACPI"); in quirk_piix4_acpi()
517 quirk_io_region(dev, 0x90, 16, PCI_BRIDGE_RESOURCES+1, "PIIX4 SMB"); in quirk_piix4_acpi()
520 pci_read_config_dword(dev, 0x5c, &res_a); in quirk_piix4_acpi()
522 piix4_io_quirk(dev, "PIIX4 devres B", 0x60, 3 << 21); in quirk_piix4_acpi()
523 piix4_io_quirk(dev, "PIIX4 devres C", 0x64, 3 << 21); in quirk_piix4_acpi()
529 piix4_io_quirk(dev, "PIIX4 devres E", 0x68, 1 << 20); in quirk_piix4_acpi()
530 piix4_mem_quirk(dev, "PIIX4 devres F", 0x6c, 1 << 7); in quirk_piix4_acpi()
534 piix4_io_quirk(dev, "PIIX4 devres G", 0x70, 1 << 20); in quirk_piix4_acpi()
535 piix4_mem_quirk(dev, "PIIX4 devres H", 0x74, 1 << 7); in quirk_piix4_acpi()
537 piix4_io_quirk(dev, "PIIX4 devres I", 0x78, 1 << 20); in quirk_piix4_acpi()
538 piix4_io_quirk(dev, "PIIX4 devres J", 0x7c, 1 << 20); in quirk_piix4_acpi()
559 static void quirk_ich4_lpc_acpi(struct pci_dev *dev) in quirk_ich4_lpc_acpi() argument
571 pci_read_config_byte(dev, ICH_ACPI_CNTL, &enable); in quirk_ich4_lpc_acpi()
573 quirk_io_region(dev, ICH_PMBASE, 128, PCI_BRIDGE_RESOURCES, in quirk_ich4_lpc_acpi()
576 pci_read_config_byte(dev, ICH4_GPIO_CNTL, &enable); in quirk_ich4_lpc_acpi()
578 quirk_io_region(dev, ICH4_GPIOBASE, 64, PCI_BRIDGE_RESOURCES+1, in quirk_ich4_lpc_acpi()
592 static void ich6_lpc_acpi_gpio(struct pci_dev *dev) in ich6_lpc_acpi_gpio() argument
596 pci_read_config_byte(dev, ICH_ACPI_CNTL, &enable); in ich6_lpc_acpi_gpio()
598 quirk_io_region(dev, ICH_PMBASE, 128, PCI_BRIDGE_RESOURCES, in ich6_lpc_acpi_gpio()
601 pci_read_config_byte(dev, ICH6_GPIO_CNTL, &enable); in ich6_lpc_acpi_gpio()
603 quirk_io_region(dev, ICH6_GPIOBASE, 64, PCI_BRIDGE_RESOURCES+1, in ich6_lpc_acpi_gpio()
607 static void ich6_lpc_generic_decode(struct pci_dev *dev, unsigned reg, const char *name, int dynsiz… in ich6_lpc_generic_decode() argument
612 pci_read_config_dword(dev, reg, &val); in ich6_lpc_generic_decode()
632 dev_info(&dev->dev, "%s PIO at %04x-%04x\n", name, base, base+size-1); in ich6_lpc_generic_decode()
635 static void quirk_ich6_lpc(struct pci_dev *dev) in quirk_ich6_lpc() argument
638 ich6_lpc_acpi_gpio(dev); in quirk_ich6_lpc()
641 ich6_lpc_generic_decode(dev, 0x84, "LPC Generic IO decode 1", 0); in quirk_ich6_lpc()
642 ich6_lpc_generic_decode(dev, 0x88, "LPC Generic IO decode 2", 1); in quirk_ich6_lpc()
647 static void ich7_lpc_generic_decode(struct pci_dev *dev, unsigned reg, const char *name) in ich7_lpc_generic_decode() argument
652 pci_read_config_dword(dev, reg, &val); in ich7_lpc_generic_decode()
667 dev_info(&dev->dev, "%s PIO at %04x (mask %04x)\n", name, base, mask); in ich7_lpc_generic_decode()
671 static void quirk_ich7_lpc(struct pci_dev *dev) in quirk_ich7_lpc() argument
674 ich6_lpc_acpi_gpio(dev); in quirk_ich7_lpc()
677 ich7_lpc_generic_decode(dev, 0x84, "ICH7 LPC Generic IO decode 1"); in quirk_ich7_lpc()
678 ich7_lpc_generic_decode(dev, 0x88, "ICH7 LPC Generic IO decode 2"); in quirk_ich7_lpc()
679 ich7_lpc_generic_decode(dev, 0x8c, "ICH7 LPC Generic IO decode 3"); in quirk_ich7_lpc()
680 ich7_lpc_generic_decode(dev, 0x90, "ICH7 LPC Generic IO decode 4"); in quirk_ich7_lpc()
700 static void quirk_vt82c586_acpi(struct pci_dev *dev) in quirk_vt82c586_acpi() argument
702 if (dev->revision & 0x10) in quirk_vt82c586_acpi()
703 quirk_io_region(dev, 0x48, 256, PCI_BRIDGE_RESOURCES, in quirk_vt82c586_acpi()
714 static void quirk_vt82c686_acpi(struct pci_dev *dev) in quirk_vt82c686_acpi() argument
716 quirk_vt82c586_acpi(dev); in quirk_vt82c686_acpi()
718 quirk_io_region(dev, 0x70, 128, PCI_BRIDGE_RESOURCES+1, in quirk_vt82c686_acpi()
721 quirk_io_region(dev, 0x90, 16, PCI_BRIDGE_RESOURCES+2, "vt82c686 SMB"); in quirk_vt82c686_acpi()
730 static void quirk_vt8235_acpi(struct pci_dev *dev) in quirk_vt8235_acpi() argument
732 quirk_io_region(dev, 0x88, 128, PCI_BRIDGE_RESOURCES, "vt8235 PM"); in quirk_vt8235_acpi()
733 quirk_io_region(dev, 0xd0, 16, PCI_BRIDGE_RESOURCES+1, "vt8235 SMB"); in quirk_vt8235_acpi()
741 static void quirk_xio2000a(struct pci_dev *dev) in quirk_xio2000a() argument
746 …dev_warn(&dev->dev, "TI XIO2000a quirk detected; secondary bus fast back-to-back transfers disable… in quirk_xio2000a()
747 list_for_each_entry(pdev, &dev->subordinate->devices, bus_list) { in quirk_xio2000a()
767 static void quirk_via_ioapic(struct pci_dev *dev) in quirk_via_ioapic() argument
776 dev_info(&dev->dev, "%sbling VIA external APIC routing\n", in quirk_via_ioapic()
780 pci_write_config_byte(dev, 0x58, tmp); in quirk_via_ioapic()
791 static void quirk_via_vt8237_bypass_apic_deassert(struct pci_dev *dev) in quirk_via_vt8237_bypass_apic_deassert() argument
796 pci_read_config_byte(dev, 0x5B, &misc_control2); in quirk_via_vt8237_bypass_apic_deassert()
798 dev_info(&dev->dev, "Bypassing VIA 8237 APIC De-Assert Message\n"); in quirk_via_vt8237_bypass_apic_deassert()
799 pci_write_config_byte(dev, 0x5B, misc_control2|BYPASS_APIC_DEASSERT); in quirk_via_vt8237_bypass_apic_deassert()
814 static void quirk_amd_ioapic(struct pci_dev *dev) in quirk_amd_ioapic() argument
816 if (dev->revision >= 0x02) { in quirk_amd_ioapic()
817 …dev_warn(&dev->dev, "I/O APIC: AMD Erratum #22 may be present. In the event of instability try\n"); in quirk_amd_ioapic()
818 dev_warn(&dev->dev, " : booting with the \"noapic\" option\n"); in quirk_amd_ioapic()
823 static void quirk_ioapic_rmw(struct pci_dev *dev) in quirk_ioapic_rmw() argument
825 if (dev->devfn == 0 && dev->bus->number == 0) in quirk_ioapic_rmw()
835 static void quirk_amd_8131_mmrbc(struct pci_dev *dev) in quirk_amd_8131_mmrbc() argument
837 if (dev->subordinate && dev->revision <= 0x12) { in quirk_amd_8131_mmrbc()
838 dev_info(&dev->dev, "AMD8131 rev %x detected; disabling PCI-X MMRBC\n", in quirk_amd_8131_mmrbc()
839 dev->revision); in quirk_amd_8131_mmrbc()
840 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MMRBC; in quirk_amd_8131_mmrbc()
874 static void quirk_via_bridge(struct pci_dev *dev) in quirk_via_bridge() argument
877 switch (dev->device) { in quirk_via_bridge()
882 via_vlink_dev_lo = PCI_SLOT(dev->devfn); in quirk_via_bridge()
883 via_vlink_dev_hi = PCI_SLOT(dev->devfn); in quirk_via_bridge()
922 static void quirk_via_vlink(struct pci_dev *dev) in quirk_via_vlink() argument
930 new_irq = dev->irq; in quirk_via_vlink()
937 if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) > via_vlink_dev_hi || in quirk_via_vlink()
938 PCI_SLOT(dev->devfn) < via_vlink_dev_lo) in quirk_via_vlink()
944 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq); in quirk_via_vlink()
946 dev_info(&dev->dev, "VIA VLink IRQ fixup, from %d to %d\n", in quirk_via_vlink()
949 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, new_irq); in quirk_via_vlink()
960 static void quirk_vt82c598_id(struct pci_dev *dev) in quirk_vt82c598_id() argument
962 pci_write_config_byte(dev, 0xfc, 0); in quirk_vt82c598_id()
963 pci_read_config_word(dev, PCI_DEVICE_ID, &dev->device); in quirk_vt82c598_id()
973 static void quirk_cardbus_legacy(struct pci_dev *dev) in quirk_cardbus_legacy() argument
975 pci_write_config_dword(dev, PCI_CB_LEGACY_MODE_BASE, 0); in quirk_cardbus_legacy()
989 static void quirk_amd_ordering(struct pci_dev *dev) in quirk_amd_ordering() argument
992 pci_read_config_dword(dev, 0x4C, &pcic); in quirk_amd_ordering()
995 dev_warn(&dev->dev, "BIOS failed to enable PCI standards compliance; fixing this error\n"); in quirk_amd_ordering()
996 pci_write_config_dword(dev, 0x4C, pcic); in quirk_amd_ordering()
997 pci_read_config_dword(dev, 0x84, &pcic); in quirk_amd_ordering()
999 pci_write_config_dword(dev, 0x84, pcic); in quirk_amd_ordering()
1012 static void quirk_dunord(struct pci_dev *dev) in quirk_dunord() argument
1014 struct resource *r = &dev->resource[1]; in quirk_dunord()
1028 static void quirk_transparent_bridge(struct pci_dev *dev) in quirk_transparent_bridge() argument
1030 dev->transparent = 1; in quirk_transparent_bridge()
1041 static void quirk_mediagx_master(struct pci_dev *dev) in quirk_mediagx_master() argument
1045 pci_read_config_byte(dev, 0x41, ®); in quirk_mediagx_master()
1048 dev_info(&dev->dev, "Fixup for MediaGX/Geode Slave Disconnect Boundary (0x41=0x%02x)\n", in quirk_mediagx_master()
1050 pci_write_config_byte(dev, 0x41, reg); in quirk_mediagx_master()
1071 dev_info(&pdev->dev, "C0 revision 450NX. Disabling PCI restreaming\n"); in quirk_disable_pxb()
1091 dev_info(&pdev->dev, "set SATA to AHCI mode\n"); in quirk_amd_ide_mode()
1129 dev_info(&pdev->dev, "IDE mode mismatch; forcing legacy mode\n"); in quirk_ide_samemode()
1161 static void quirk_eisa_bridge(struct pci_dev *dev) in quirk_eisa_bridge() argument
1163 dev->class = PCI_CLASS_BRIDGE_EISA << 8; in quirk_eisa_bridge()
1195 static void asus_hides_smbus_hostbridge(struct pci_dev *dev) in asus_hides_smbus_hostbridge() argument
1197 if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) { in asus_hides_smbus_hostbridge()
1198 if (dev->device == PCI_DEVICE_ID_INTEL_82845_HB) in asus_hides_smbus_hostbridge()
1199 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1206 else if (dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) in asus_hides_smbus_hostbridge()
1207 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1213 else if (dev->device == PCI_DEVICE_ID_INTEL_82850_HB) in asus_hides_smbus_hostbridge()
1214 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1218 else if (dev->device == PCI_DEVICE_ID_INTEL_7205_0) in asus_hides_smbus_hostbridge()
1219 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1223 else if (dev->device == PCI_DEVICE_ID_INTEL_E7501_MCH) in asus_hides_smbus_hostbridge()
1224 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1228 else if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB) in asus_hides_smbus_hostbridge()
1229 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1235 else if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) in asus_hides_smbus_hostbridge()
1236 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1241 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB) in asus_hides_smbus_hostbridge()
1242 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1246 else if (dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB) in asus_hides_smbus_hostbridge()
1247 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1252 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_HP)) { in asus_hides_smbus_hostbridge()
1253 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) in asus_hides_smbus_hostbridge()
1254 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1259 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB) in asus_hides_smbus_hostbridge()
1260 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1266 else if (dev->device == PCI_DEVICE_ID_INTEL_82875_HB) in asus_hides_smbus_hostbridge()
1267 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1271 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG)) { in asus_hides_smbus_hostbridge()
1272 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) in asus_hides_smbus_hostbridge()
1273 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1277 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ)) { in asus_hides_smbus_hostbridge()
1278 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) in asus_hides_smbus_hostbridge()
1279 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1283 else if (dev->device == PCI_DEVICE_ID_INTEL_82810_IG3) in asus_hides_smbus_hostbridge()
1284 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1291 else if (dev->device == PCI_DEVICE_ID_INTEL_82801DB_2) in asus_hides_smbus_hostbridge()
1292 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1303 else if (dev->device == PCI_DEVICE_ID_INTEL_82815_CGC) in asus_hides_smbus_hostbridge()
1304 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1328 static void asus_hides_smbus_lpc(struct pci_dev *dev) in asus_hides_smbus_lpc() argument
1335 pci_read_config_word(dev, 0xF2, &val); in asus_hides_smbus_lpc()
1337 pci_write_config_word(dev, 0xF2, val & (~0x8)); in asus_hides_smbus_lpc()
1338 pci_read_config_word(dev, 0xF2, &val); in asus_hides_smbus_lpc()
1340 dev_info(&dev->dev, "i801 SMBus device continues to play 'hide and seek'! 0x%x\n", in asus_hides_smbus_lpc()
1343 dev_info(&dev->dev, "Enabled i801 SMBus device\n"); in asus_hides_smbus_lpc()
1363 static void asus_hides_smbus_lpc_ich6_suspend(struct pci_dev *dev) in asus_hides_smbus_lpc_ich6_suspend() argument
1371 pci_read_config_dword(dev, 0xF0, &rcba); in asus_hides_smbus_lpc_ich6_suspend()
1378 static void asus_hides_smbus_lpc_ich6_resume_early(struct pci_dev *dev) in asus_hides_smbus_lpc_ich6_resume_early() argument
1389 static void asus_hides_smbus_lpc_ich6_resume(struct pci_dev *dev) in asus_hides_smbus_lpc_ich6_resume() argument
1395 dev_info(&dev->dev, "Enabled ICH6/i801 SMBus device\n"); in asus_hides_smbus_lpc_ich6_resume()
1398 static void asus_hides_smbus_lpc_ich6(struct pci_dev *dev) in asus_hides_smbus_lpc_ich6() argument
1400 asus_hides_smbus_lpc_ich6_suspend(dev); in asus_hides_smbus_lpc_ich6()
1401 asus_hides_smbus_lpc_ich6_resume_early(dev); in asus_hides_smbus_lpc_ich6()
1402 asus_hides_smbus_lpc_ich6_resume(dev); in asus_hides_smbus_lpc_ich6()
1412 static void quirk_sis_96x_smbus(struct pci_dev *dev) in quirk_sis_96x_smbus() argument
1415 pci_read_config_byte(dev, 0x77, &val); in quirk_sis_96x_smbus()
1417 dev_info(&dev->dev, "Enabling SiS 96x SMBus\n"); in quirk_sis_96x_smbus()
1418 pci_write_config_byte(dev, 0x77, val & ~0x10); in quirk_sis_96x_smbus()
1440 static void quirk_sis_503(struct pci_dev *dev) in quirk_sis_503() argument
1445 pci_read_config_byte(dev, SIS_DETECT_REGISTER, ®); in quirk_sis_503()
1446 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg | (1 << 6)); in quirk_sis_503()
1447 pci_read_config_word(dev, PCI_DEVICE_ID, &devid); in quirk_sis_503()
1449 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg); in quirk_sis_503()
1458 dev->device = devid; in quirk_sis_503()
1459 quirk_sis_96x_smbus(dev); in quirk_sis_503()
1471 static void asus_hides_ac97_lpc(struct pci_dev *dev) in asus_hides_ac97_lpc() argument
1476 if (likely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) { in asus_hides_ac97_lpc()
1477 if (dev->device == PCI_DEVICE_ID_VIA_8237) in asus_hides_ac97_lpc()
1484 pci_read_config_byte(dev, 0x50, &val); in asus_hides_ac97_lpc()
1486 pci_write_config_byte(dev, 0x50, val & (~0xc0)); in asus_hides_ac97_lpc()
1487 pci_read_config_byte(dev, 0x50, &val); in asus_hides_ac97_lpc()
1489 dev_info(&dev->dev, "Onboard AC97/MC97 devices continue to play 'hide and seek'! 0x%x\n", in asus_hides_ac97_lpc()
1492 dev_info(&dev->dev, "Enabled onboard AC97/MC97 devices\n"); in asus_hides_ac97_lpc()
1579 static void quirk_jmicron_async_suspend(struct pci_dev *dev) in quirk_jmicron_async_suspend() argument
1581 if (dev->multifunction) { in quirk_jmicron_async_suspend()
1582 device_disable_async_suspend(&dev->dev); in quirk_jmicron_async_suspend()
1583 dev_info(&dev->dev, "async suspend disabled to avoid multi-function power-on ordering issue\n"); in quirk_jmicron_async_suspend()
1627 static void quirk_pcie_pxh(struct pci_dev *dev) in quirk_pcie_pxh() argument
1629 pci_msi_off(dev); in quirk_pcie_pxh()
1630 dev->no_msi = 1; in quirk_pcie_pxh()
1631 dev_warn(&dev->dev, "PXH quirk detected; SHPC device MSI disabled\n"); in quirk_pcie_pxh()
1643 static void quirk_intel_pcie_pm(struct pci_dev *dev) in quirk_intel_pcie_pm() argument
1646 dev->no_d1d2 = 1; in quirk_intel_pcie_pm()
1678 static void quirk_reroute_to_boot_interrupts_intel(struct pci_dev *dev) in quirk_reroute_to_boot_interrupts_intel() argument
1683 dev->irq_reroute_variant = INTEL_IRQ_REROUTE_VARIANT; in quirk_reroute_to_boot_interrupts_intel()
1684 dev_info(&dev->dev, "rerouting interrupts for [%04x:%04x]\n", in quirk_reroute_to_boot_interrupts_intel()
1685 dev->vendor, dev->device); in quirk_reroute_to_boot_interrupts_intel()
1716 static void quirk_disable_intel_boot_interrupt(struct pci_dev *dev) in quirk_disable_intel_boot_interrupt() argument
1723 pci_read_config_word(dev, INTEL_6300_IOAPIC_ABAR, &pci_config_word); in quirk_disable_intel_boot_interrupt()
1725 pci_write_config_word(dev, INTEL_6300_IOAPIC_ABAR, pci_config_word); in quirk_disable_intel_boot_interrupt()
1727 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n", in quirk_disable_intel_boot_interrupt()
1728 dev->vendor, dev->device); in quirk_disable_intel_boot_interrupt()
1741 static void quirk_disable_broadcom_boot_interrupt(struct pci_dev *dev) in quirk_disable_broadcom_boot_interrupt() argument
1749 pci_read_config_dword(dev, BC_HT1000_FEATURE_REG, &pci_config_dword); in quirk_disable_broadcom_boot_interrupt()
1750 pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword | in quirk_disable_broadcom_boot_interrupt()
1758 pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword); in quirk_disable_broadcom_boot_interrupt()
1760 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n", in quirk_disable_broadcom_boot_interrupt()
1761 dev->vendor, dev->device); in quirk_disable_broadcom_boot_interrupt()
1779 static void quirk_disable_amd_813x_boot_interrupt(struct pci_dev *dev) in quirk_disable_amd_813x_boot_interrupt() argument
1785 if ((dev->revision == AMD_813X_REV_B1) || in quirk_disable_amd_813x_boot_interrupt()
1786 (dev->revision == AMD_813X_REV_B2)) in quirk_disable_amd_813x_boot_interrupt()
1789 pci_read_config_dword(dev, AMD_813X_MISC, &pci_config_dword); in quirk_disable_amd_813x_boot_interrupt()
1791 pci_write_config_dword(dev, AMD_813X_MISC, pci_config_dword); in quirk_disable_amd_813x_boot_interrupt()
1793 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n", in quirk_disable_amd_813x_boot_interrupt()
1794 dev->vendor, dev->device); in quirk_disable_amd_813x_boot_interrupt()
1803 static void quirk_disable_amd_8111_boot_interrupt(struct pci_dev *dev) in quirk_disable_amd_8111_boot_interrupt() argument
1810 pci_read_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, &pci_config_word); in quirk_disable_amd_8111_boot_interrupt()
1812 dev_info(&dev->dev, "boot interrupts on device [%04x:%04x] already disabled\n", in quirk_disable_amd_8111_boot_interrupt()
1813 dev->vendor, dev->device); in quirk_disable_amd_8111_boot_interrupt()
1816 pci_write_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, 0); in quirk_disable_amd_8111_boot_interrupt()
1817 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n", in quirk_disable_amd_8111_boot_interrupt()
1818 dev->vendor, dev->device); in quirk_disable_amd_8111_boot_interrupt()
1829 static void quirk_tc86c001_ide(struct pci_dev *dev) in quirk_tc86c001_ide() argument
1831 struct resource *r = &dev->resource[0]; in quirk_tc86c001_ide()
1850 static void quirk_plx_pci9050(struct pci_dev *dev) in quirk_plx_pci9050() argument
1855 if (dev->revision >= 2) in quirk_plx_pci9050()
1858 if (pci_resource_len(dev, bar) == 0x80 && in quirk_plx_pci9050()
1859 (pci_resource_start(dev, bar) & 0x80)) { in quirk_plx_pci9050()
1860 struct resource *r = &dev->resource[bar]; in quirk_plx_pci9050()
1861 dev_info(&dev->dev, "Re-allocating PLX PCI 9050 BAR %u to length 256 to avoid bit 7 bug\n", in quirk_plx_pci9050()
1882 static void quirk_netmos(struct pci_dev *dev) in quirk_netmos() argument
1884 unsigned int num_parallel = (dev->subsystem_device & 0xf0) >> 4; in quirk_netmos()
1885 unsigned int num_serial = dev->subsystem_device & 0xf; in quirk_netmos()
1897 switch (dev->device) { in quirk_netmos()
1900 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM && in quirk_netmos()
1901 dev->subsystem_device == 0x0299) in quirk_netmos()
1908 …dev_info(&dev->dev, "Netmos %04x (%u parallel, %u serial); changing class SERIAL to OTHER (use par… in quirk_netmos()
1909 dev->device, num_parallel, num_serial); in quirk_netmos()
1910 dev->class = (PCI_CLASS_COMMUNICATION_OTHER << 8) | in quirk_netmos()
1911 (dev->class & 0xff); in quirk_netmos()
1923 static void quirk_f0_vpd_link(struct pci_dev *dev) in quirk_f0_vpd_link() argument
1927 if (!PCI_FUNC(dev->devfn)) in quirk_f0_vpd_link()
1930 f0 = pci_get_slot(dev->bus, PCI_DEVFN(PCI_SLOT(dev->devfn), 0)); in quirk_f0_vpd_link()
1934 if (f0->vpd && dev->class == f0->class && in quirk_f0_vpd_link()
1935 dev->vendor == f0->vendor && dev->device == f0->device) in quirk_f0_vpd_link()
1936 dev->dev_flags |= PCI_DEV_FLAGS_VPD_REF_F0; in quirk_f0_vpd_link()
1943 static void quirk_e100_interrupt(struct pci_dev *dev) in quirk_e100_interrupt() argument
1949 switch (dev->device) { in quirk_e100_interrupt()
1976 pci_read_config_word(dev, PCI_COMMAND, &command); in quirk_e100_interrupt()
1978 if (!(command & PCI_COMMAND_MEMORY) || !pci_resource_start(dev, 0)) in quirk_e100_interrupt()
1985 if (dev->pm_cap) { in quirk_e100_interrupt()
1986 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); in quirk_e100_interrupt()
1992 csr = ioremap(pci_resource_start(dev, 0), 8); in quirk_e100_interrupt()
1994 dev_warn(&dev->dev, "Can't map e100 registers\n"); in quirk_e100_interrupt()
2000 dev_warn(&dev->dev, "Firmware left e100 interrupts enabled; disabling\n"); in quirk_e100_interrupt()
2013 static void quirk_disable_aspm_l0s(struct pci_dev *dev) in quirk_disable_aspm_l0s() argument
2015 dev_info(&dev->dev, "Disabling L0s\n"); in quirk_disable_aspm_l0s()
2016 pci_disable_link_state(dev, PCIE_LINK_STATE_L0S); in quirk_disable_aspm_l0s()
2033 static void fixup_rev1_53c810(struct pci_dev *dev) in fixup_rev1_53c810() argument
2039 if (dev->class == PCI_CLASS_NOT_DEFINED) { in fixup_rev1_53c810()
2040 dev_info(&dev->dev, "NCR 53c810 rev 1 detected; setting PCI class\n"); in fixup_rev1_53c810()
2041 dev->class = PCI_CLASS_STORAGE_SCSI; in fixup_rev1_53c810()
2047 static void quirk_p64h2_1k_io(struct pci_dev *dev) in quirk_p64h2_1k_io() argument
2051 pci_read_config_word(dev, 0x40, &en1k); in quirk_p64h2_1k_io()
2054 dev_info(&dev->dev, "Enable I/O Space to 1KB granularity\n"); in quirk_p64h2_1k_io()
2055 dev->io_window_1k = 1; in quirk_p64h2_1k_io()
2064 static void quirk_nvidia_ck804_pcie_aer_ext_cap(struct pci_dev *dev) in quirk_nvidia_ck804_pcie_aer_ext_cap() argument
2067 if (pci_read_config_byte(dev, 0xf41, &b) == 0) { in quirk_nvidia_ck804_pcie_aer_ext_cap()
2069 pci_write_config_byte(dev, 0xf41, b | 0x20); in quirk_nvidia_ck804_pcie_aer_ext_cap()
2070 dev_info(&dev->dev, "Linking AER extended capability\n"); in quirk_nvidia_ck804_pcie_aer_ext_cap()
2079 static void quirk_via_cx700_pci_parking_caching(struct pci_dev *dev) in quirk_via_cx700_pci_parking_caching() argument
2103 if (pci_read_config_byte(dev, 0x76, &b) == 0) { in quirk_via_cx700_pci_parking_caching()
2106 pci_write_config_byte(dev, 0x76, b ^ 0x40); in quirk_via_cx700_pci_parking_caching()
2108 dev_info(&dev->dev, "Disabling VIA CX700 PCI parking\n"); in quirk_via_cx700_pci_parking_caching()
2112 if (pci_read_config_byte(dev, 0x72, &b) == 0) { in quirk_via_cx700_pci_parking_caching()
2115 pci_write_config_byte(dev, 0x72, 0x0); in quirk_via_cx700_pci_parking_caching()
2118 pci_write_config_byte(dev, 0x75, 0x1); in quirk_via_cx700_pci_parking_caching()
2121 pci_write_config_byte(dev, 0x77, 0x0); in quirk_via_cx700_pci_parking_caching()
2123 dev_info(&dev->dev, "Disabling VIA CX700 PCI caching\n"); in quirk_via_cx700_pci_parking_caching()
2140 static void quirk_brcm_570x_limit_vpd(struct pci_dev *dev) in quirk_brcm_570x_limit_vpd() argument
2146 if ((dev->device == PCI_DEVICE_ID_NX2_5706) || in quirk_brcm_570x_limit_vpd()
2147 (dev->device == PCI_DEVICE_ID_NX2_5706S) || in quirk_brcm_570x_limit_vpd()
2148 (dev->device == PCI_DEVICE_ID_NX2_5708) || in quirk_brcm_570x_limit_vpd()
2149 (dev->device == PCI_DEVICE_ID_NX2_5708S) || in quirk_brcm_570x_limit_vpd()
2150 ((dev->device == PCI_DEVICE_ID_NX2_5709) && in quirk_brcm_570x_limit_vpd()
2151 (dev->revision & 0xf0) == 0x0)) { in quirk_brcm_570x_limit_vpd()
2152 if (dev->vpd) in quirk_brcm_570x_limit_vpd()
2153 dev->vpd->len = 0x80; in quirk_brcm_570x_limit_vpd()
2176 static void quirk_brcm_5719_limit_mrrs(struct pci_dev *dev) in quirk_brcm_5719_limit_mrrs() argument
2180 pci_read_config_dword(dev, 0xf4, &rev); in quirk_brcm_5719_limit_mrrs()
2184 int readrq = pcie_get_readrq(dev); in quirk_brcm_5719_limit_mrrs()
2186 pcie_set_readrq(dev, 2048); in quirk_brcm_5719_limit_mrrs()
2200 static void quirk_unhide_mch_dev6(struct pci_dev *dev) in quirk_unhide_mch_dev6() argument
2204 if (pci_read_config_byte(dev, 0xF4, ®) == 0 && !(reg & 0x02)) { in quirk_unhide_mch_dev6()
2205 dev_info(&dev->dev, "Enabling MCH 'Overflow' Device\n"); in quirk_unhide_mch_dev6()
2206 pci_write_config_byte(dev, 0xF4, reg | 0x02); in quirk_unhide_mch_dev6()
2224 static void quirk_tile_plx_gen1(struct pci_dev *dev) in quirk_tile_plx_gen1() argument
2227 pci_write_config_dword(dev, 0x98, 0x1); in quirk_tile_plx_gen1()
2241 static void quirk_disable_all_msi(struct pci_dev *dev) in quirk_disable_all_msi() argument
2244 dev_warn(&dev->dev, "MSI quirk detected; MSI disabled\n"); in quirk_disable_all_msi()
2255 static void quirk_disable_msi(struct pci_dev *dev) in quirk_disable_msi() argument
2257 if (dev->subordinate) { in quirk_disable_msi()
2258 dev_warn(&dev->dev, "MSI quirk detected; subordinate MSI disabled\n"); in quirk_disable_msi()
2259 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI; in quirk_disable_msi()
2288 static int msi_ht_cap_enabled(struct pci_dev *dev) in msi_ht_cap_enabled() argument
2292 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING); in msi_ht_cap_enabled()
2296 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS, in msi_ht_cap_enabled()
2298 dev_info(&dev->dev, "Found %s HT MSI Mapping\n", in msi_ht_cap_enabled()
2304 pos = pci_find_next_ht_capability(dev, pos, in msi_ht_cap_enabled()
2311 static void quirk_msi_ht_cap(struct pci_dev *dev) in quirk_msi_ht_cap() argument
2313 if (dev->subordinate && !msi_ht_cap_enabled(dev)) { in quirk_msi_ht_cap()
2314 dev_warn(&dev->dev, "MSI quirk detected; subordinate MSI disabled\n"); in quirk_msi_ht_cap()
2315 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI; in quirk_msi_ht_cap()
2324 static void quirk_nvidia_ck804_msi_ht_cap(struct pci_dev *dev) in quirk_nvidia_ck804_msi_ht_cap() argument
2328 if (!dev->subordinate) in quirk_nvidia_ck804_msi_ht_cap()
2334 pdev = pci_get_slot(dev->bus, 0); in quirk_nvidia_ck804_msi_ht_cap()
2337 if (!msi_ht_cap_enabled(dev) && !msi_ht_cap_enabled(pdev)) { in quirk_nvidia_ck804_msi_ht_cap()
2338 dev_warn(&dev->dev, "MSI quirk detected; subordinate MSI disabled\n"); in quirk_nvidia_ck804_msi_ht_cap()
2339 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI; in quirk_nvidia_ck804_msi_ht_cap()
2347 static void ht_enable_msi_mapping(struct pci_dev *dev) in ht_enable_msi_mapping() argument
2351 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING); in ht_enable_msi_mapping()
2355 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS, in ht_enable_msi_mapping()
2357 dev_info(&dev->dev, "Enabling HT MSI Mapping\n"); in ht_enable_msi_mapping()
2359 pci_write_config_byte(dev, pos + HT_MSI_FLAGS, in ht_enable_msi_mapping()
2362 pos = pci_find_next_ht_capability(dev, pos, in ht_enable_msi_mapping()
2377 static void nvenet_msi_disable(struct pci_dev *dev) in nvenet_msi_disable() argument
2384 dev_info(&dev->dev, "Disabling msi for MCP55 NIC on P5N32-SLI\n"); in nvenet_msi_disable()
2385 dev->no_msi = 1; in nvenet_msi_disable()
2402 static void nvbridge_check_legacy_irq_routing(struct pci_dev *dev) in nvbridge_check_legacy_irq_routing() argument
2406 if (!pci_find_capability(dev, PCI_CAP_ID_HT)) in nvbridge_check_legacy_irq_routing()
2409 pci_read_config_dword(dev, 0x74, &cfg); in nvbridge_check_legacy_irq_routing()
2414 pci_write_config_dword(dev, 0x74, cfg); in nvbridge_check_legacy_irq_routing()
2426 static int ht_check_msi_mapping(struct pci_dev *dev) in ht_check_msi_mapping() argument
2432 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING); in ht_check_msi_mapping()
2438 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS, in ht_check_msi_mapping()
2447 pos = pci_find_next_ht_capability(dev, pos, in ht_check_msi_mapping()
2456 struct pci_dev *dev; in host_bridge_with_leaf() local
2463 dev = pci_get_slot(host_bridge->bus, PCI_DEVFN(i, 0)); in host_bridge_with_leaf()
2464 if (!dev) in host_bridge_with_leaf()
2468 pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE); in host_bridge_with_leaf()
2470 pci_dev_put(dev); in host_bridge_with_leaf()
2474 if (ht_check_msi_mapping(dev)) { in host_bridge_with_leaf()
2476 pci_dev_put(dev); in host_bridge_with_leaf()
2479 pci_dev_put(dev); in host_bridge_with_leaf()
2488 static int is_end_of_ht_chain(struct pci_dev *dev) in is_end_of_ht_chain() argument
2494 pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE); in is_end_of_ht_chain()
2499 pci_read_config_word(dev, pos + PCI_CAP_FLAGS, &flags); in is_end_of_ht_chain()
2503 pci_read_config_word(dev, pos + ctrl_off, &ctrl); in is_end_of_ht_chain()
2512 static void nv_ht_enable_msi_mapping(struct pci_dev *dev) in nv_ht_enable_msi_mapping() argument
2519 dev_no = dev->devfn >> 3; in nv_ht_enable_msi_mapping()
2521 host_bridge = pci_get_slot(dev->bus, PCI_DEVFN(i, 0)); in nv_ht_enable_msi_mapping()
2537 if (host_bridge == dev && is_end_of_ht_chain(host_bridge) && in nv_ht_enable_msi_mapping()
2545 ht_enable_msi_mapping(dev); in nv_ht_enable_msi_mapping()
2551 static void ht_disable_msi_mapping(struct pci_dev *dev) in ht_disable_msi_mapping() argument
2555 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING); in ht_disable_msi_mapping()
2559 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS, in ht_disable_msi_mapping()
2561 dev_info(&dev->dev, "Disabling HT MSI Mapping\n"); in ht_disable_msi_mapping()
2563 pci_write_config_byte(dev, pos + HT_MSI_FLAGS, in ht_disable_msi_mapping()
2566 pos = pci_find_next_ht_capability(dev, pos, in ht_disable_msi_mapping()
2571 static void __nv_msi_ht_cap_quirk(struct pci_dev *dev, int all) in __nv_msi_ht_cap_quirk() argument
2581 found = ht_check_msi_mapping(dev); in __nv_msi_ht_cap_quirk()
2593 dev_warn(&dev->dev, "nv_msi_ht_cap_quirk didn't locate host bridge\n"); in __nv_msi_ht_cap_quirk()
2603 ht_enable_msi_mapping(dev); in __nv_msi_ht_cap_quirk()
2605 nv_ht_enable_msi_mapping(dev); in __nv_msi_ht_cap_quirk()
2615 ht_disable_msi_mapping(dev); in __nv_msi_ht_cap_quirk()
2621 static void nv_msi_ht_cap_quirk_all(struct pci_dev *dev) in nv_msi_ht_cap_quirk_all() argument
2623 return __nv_msi_ht_cap_quirk(dev, 1); in nv_msi_ht_cap_quirk_all()
2626 static void nv_msi_ht_cap_quirk_leaf(struct pci_dev *dev) in nv_msi_ht_cap_quirk_leaf() argument
2628 return __nv_msi_ht_cap_quirk(dev, 0); in nv_msi_ht_cap_quirk_leaf()
2637 static void quirk_msi_intx_disable_bug(struct pci_dev *dev) in quirk_msi_intx_disable_bug() argument
2639 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG; in quirk_msi_intx_disable_bug()
2641 static void quirk_msi_intx_disable_ati_bug(struct pci_dev *dev) in quirk_msi_intx_disable_ati_bug() argument
2655 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG; in quirk_msi_intx_disable_ati_bug()
2658 static void quirk_msi_intx_disable_qca_bug(struct pci_dev *dev) in quirk_msi_intx_disable_qca_bug() argument
2661 if (dev->revision < 0x18) { in quirk_msi_intx_disable_qca_bug()
2662 dev_info(&dev->dev, "set MSI_INTX_DISABLE_BUG flag\n"); in quirk_msi_intx_disable_qca_bug()
2663 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG; in quirk_msi_intx_disable_qca_bug()
2733 static void quirk_hotplug_bridge(struct pci_dev *dev) in quirk_hotplug_bridge() argument
2735 dev->is_hotplug_bridge = 1; in quirk_hotplug_bridge()
2768 static void ricoh_mmc_fixup_rl5c476(struct pci_dev *dev) in ricoh_mmc_fixup_rl5c476() argument
2776 if (PCI_FUNC(dev->devfn)) in ricoh_mmc_fixup_rl5c476()
2779 pci_read_config_byte(dev, 0xB7, &disable); in ricoh_mmc_fixup_rl5c476()
2783 pci_read_config_byte(dev, 0x8E, &write_enable); in ricoh_mmc_fixup_rl5c476()
2784 pci_write_config_byte(dev, 0x8E, 0xAA); in ricoh_mmc_fixup_rl5c476()
2785 pci_read_config_byte(dev, 0x8D, &write_target); in ricoh_mmc_fixup_rl5c476()
2786 pci_write_config_byte(dev, 0x8D, 0xB7); in ricoh_mmc_fixup_rl5c476()
2787 pci_write_config_byte(dev, 0xB7, disable | 0x02); in ricoh_mmc_fixup_rl5c476()
2788 pci_write_config_byte(dev, 0x8E, write_enable); in ricoh_mmc_fixup_rl5c476()
2789 pci_write_config_byte(dev, 0x8D, write_target); in ricoh_mmc_fixup_rl5c476()
2791 dev_notice(&dev->dev, "proprietary Ricoh MMC controller disabled (via cardbus function)\n"); in ricoh_mmc_fixup_rl5c476()
2792 dev_notice(&dev->dev, "MMC cards are now supported by standard SDHCI controller\n"); in ricoh_mmc_fixup_rl5c476()
2797 static void ricoh_mmc_fixup_r5c832(struct pci_dev *dev) in ricoh_mmc_fixup_r5c832() argument
2804 if (PCI_FUNC(dev->devfn)) in ricoh_mmc_fixup_r5c832()
2818 if (dev->device == PCI_DEVICE_ID_RICOH_R5CE822 || in ricoh_mmc_fixup_r5c832()
2819 dev->device == PCI_DEVICE_ID_RICOH_R5CE823) { in ricoh_mmc_fixup_r5c832()
2820 pci_write_config_byte(dev, 0xf9, 0xfc); in ricoh_mmc_fixup_r5c832()
2821 pci_write_config_byte(dev, 0x150, 0x10); in ricoh_mmc_fixup_r5c832()
2822 pci_write_config_byte(dev, 0xf9, 0x00); in ricoh_mmc_fixup_r5c832()
2823 pci_write_config_byte(dev, 0xfc, 0x01); in ricoh_mmc_fixup_r5c832()
2824 pci_write_config_byte(dev, 0xe1, 0x32); in ricoh_mmc_fixup_r5c832()
2825 pci_write_config_byte(dev, 0xfc, 0x00); in ricoh_mmc_fixup_r5c832()
2827 dev_notice(&dev->dev, "MMC controller base frequency changed to 50Mhz.\n"); in ricoh_mmc_fixup_r5c832()
2830 pci_read_config_byte(dev, 0xCB, &disable); in ricoh_mmc_fixup_r5c832()
2835 pci_read_config_byte(dev, 0xCA, &write_enable); in ricoh_mmc_fixup_r5c832()
2836 pci_write_config_byte(dev, 0xCA, 0x57); in ricoh_mmc_fixup_r5c832()
2837 pci_write_config_byte(dev, 0xCB, disable | 0x02); in ricoh_mmc_fixup_r5c832()
2838 pci_write_config_byte(dev, 0xCA, write_enable); in ricoh_mmc_fixup_r5c832()
2840 dev_notice(&dev->dev, "proprietary Ricoh MMC controller disabled (via firewire function)\n"); in ricoh_mmc_fixup_r5c832()
2841 dev_notice(&dev->dev, "MMC cards are now supported by standard SDHCI controller\n"); in ricoh_mmc_fixup_r5c832()
2865 static void vtd_mask_spec_errors(struct pci_dev *dev) in vtd_mask_spec_errors() argument
2869 pci_read_config_dword(dev, VTUNCERRMSK_REG, &word); in vtd_mask_spec_errors()
2870 pci_write_config_dword(dev, VTUNCERRMSK_REG, word | VTD_MSK_SPEC_ERRORS); in vtd_mask_spec_errors()
2876 static void fixup_ti816x_class(struct pci_dev *dev) in fixup_ti816x_class() argument
2878 u32 class = dev->class; in fixup_ti816x_class()
2881 dev->class = PCI_CLASS_MULTIMEDIA_VIDEO << 8; in fixup_ti816x_class()
2882 dev_info(&dev->dev, "PCI class overridden (%#08x -> %#08x)\n", in fixup_ti816x_class()
2883 class, dev->class); in fixup_ti816x_class()
2891 static void fixup_mpss_256(struct pci_dev *dev) in fixup_mpss_256() argument
2893 dev->pcie_mpss = 1; /* 256 bytes */ in fixup_mpss_256()
2909 static void quirk_intel_mc_errata(struct pci_dev *dev) in quirk_intel_mc_errata() argument
2921 err = pci_read_config_word(dev, 0x48, &rcc); in quirk_intel_mc_errata()
2923 dev_err(&dev->dev, "Error attempting to read the read completion coalescing register\n"); in quirk_intel_mc_errata()
2932 err = pci_write_config_word(dev, 0x48, rcc); in quirk_intel_mc_errata()
2934 dev_err(&dev->dev, "Error attempting to write the read completion coalescing register\n"); in quirk_intel_mc_errata()
2974 static void quirk_intel_ntb(struct pci_dev *dev) in quirk_intel_ntb() argument
2979 rc = pci_read_config_byte(dev, 0x00D0, &val); in quirk_intel_ntb()
2983 dev->resource[2].end = dev->resource[2].start + ((u64) 1 << val) - 1; in quirk_intel_ntb()
2985 rc = pci_read_config_byte(dev, 0x00D1, &val); in quirk_intel_ntb()
2989 dev->resource[4].end = dev->resource[4].start + ((u64) 1 << val) - 1; in quirk_intel_ntb()
2994 static ktime_t fixup_debug_start(struct pci_dev *dev, in fixup_debug_start() argument
2995 void (*fn)(struct pci_dev *dev)) in fixup_debug_start() argument
2999 dev_dbg(&dev->dev, "calling %pF\n", fn); in fixup_debug_start()
3002 fn, task_pid_nr(current), dev_name(&dev->dev)); in fixup_debug_start()
3009 static void fixup_debug_report(struct pci_dev *dev, ktime_t calltime, in fixup_debug_report() argument
3010 void (*fn)(struct pci_dev *dev)) in fixup_debug_report() argument
3020 fn, duration, dev_name(&dev->dev)); in fixup_debug_report()
3037 static void disable_igfx_irq(struct pci_dev *dev) in disable_igfx_irq() argument
3039 void __iomem *regs = pci_iomap(dev, 0, 0); in disable_igfx_irq()
3041 dev_warn(&dev->dev, "igfx quirk: Can't iomap PCI device\n"); in disable_igfx_irq()
3047 dev_warn(&dev->dev, "BIOS left Intel GPU interrupts enabled; disabling\n"); in disable_igfx_irq()
3052 pci_iounmap(dev, regs); in disable_igfx_irq()
3062 static void quirk_remove_d3_delay(struct pci_dev *dev) in quirk_remove_d3_delay() argument
3064 dev->d3_delay = 0; in quirk_remove_d3_delay()
3086 static void quirk_broken_intx_masking(struct pci_dev *dev) in quirk_broken_intx_masking() argument
3088 dev->broken_intx_masking = 1; in quirk_broken_intx_masking()
3105 static void quirk_no_bus_reset(struct pci_dev *dev) in quirk_no_bus_reset() argument
3107 dev->dev_flags |= PCI_DEV_FLAGS_NO_BUS_RESET; in quirk_no_bus_reset()
3119 static void quirk_no_pm_reset(struct pci_dev *dev) in quirk_no_pm_reset() argument
3125 if (!pci_is_root_bus(dev->bus)) in quirk_no_pm_reset()
3126 dev->dev_flags |= PCI_DEV_FLAGS_NO_PM_RESET; in quirk_no_pm_reset()
3156 static void quirk_apple_poweroff_thunderbolt(struct pci_dev *dev) in quirk_apple_poweroff_thunderbolt() argument
3162 if (pci_pcie_type(dev) != PCI_EXP_TYPE_UPSTREAM) in quirk_apple_poweroff_thunderbolt()
3164 bridge = ACPI_HANDLE(&dev->dev); in quirk_apple_poweroff_thunderbolt()
3177 dev_info(&dev->dev, "quirk: cutting power to thunderbolt controller...\n"); in quirk_apple_poweroff_thunderbolt()
3199 static void quirk_apple_wait_for_thunderbolt(struct pci_dev *dev) in quirk_apple_wait_for_thunderbolt() argument
3206 if (pci_pcie_type(dev) != PCI_EXP_TYPE_DOWNSTREAM) in quirk_apple_wait_for_thunderbolt()
3212 sibling = pci_get_slot(dev->bus, 0x0); in quirk_apple_wait_for_thunderbolt()
3213 if (sibling == dev) in quirk_apple_wait_for_thunderbolt()
3225 dev_info(&dev->dev, "quirk: waiting for thunderbolt to reestablish PCI tunnels...\n"); in quirk_apple_wait_for_thunderbolt()
3226 device_pm_wait_for_dev(&dev->dev, &nhi->dev); in quirk_apple_wait_for_thunderbolt()
3237 static void pci_do_fixups(struct pci_dev *dev, struct pci_fixup *f, in pci_do_fixups() argument
3243 if ((f->class == (u32) (dev->class >> f->class_shift) || in pci_do_fixups()
3245 (f->vendor == dev->vendor || in pci_do_fixups()
3247 (f->device == dev->device || in pci_do_fixups()
3249 calltime = fixup_debug_start(dev, f->hook); in pci_do_fixups()
3250 f->hook(dev); in pci_do_fixups()
3251 fixup_debug_report(dev, calltime, f->hook); in pci_do_fixups()
3274 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev) in pci_fixup_device() argument
3325 pci_do_fixups(dev, start, end); in pci_fixup_device()
3332 struct pci_dev *dev = NULL; in pci_apply_final_quirks() local
3341 for_each_pci_dev(dev) { in pci_apply_final_quirks()
3342 pci_fixup_device(pci_fixup_final, dev); in pci_apply_final_quirks()
3349 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &tmp); in pci_apply_final_quirks()
3378 static int reset_intel_generic_dev(struct pci_dev *dev, int probe) in reset_intel_generic_dev() argument
3383 if (dev->class == PCI_CLASS_SERIAL_USB) { in reset_intel_generic_dev()
3384 pos = pci_find_capability(dev, PCI_CAP_ID_VNDR); in reset_intel_generic_dev()
3391 pci_write_config_byte(dev, pos + 0x4, 1); in reset_intel_generic_dev()
3400 static int reset_intel_82599_sfp_virtfn(struct pci_dev *dev, int probe) in reset_intel_82599_sfp_virtfn() argument
3413 if (!pci_wait_for_pending_transaction(dev)) in reset_intel_82599_sfp_virtfn()
3414 dev_err(&dev->dev, "transaction is not cleared; proceeding with reset anyway\n"); in reset_intel_82599_sfp_virtfn()
3416 pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR); in reset_intel_82599_sfp_virtfn()
3428 static int reset_ivb_igd(struct pci_dev *dev, int probe) in reset_ivb_igd() argument
3437 mmio_base = pci_iomap(dev, 0, 0); in reset_ivb_igd()
3461 dev_warn(&dev->dev, "timeout during reset\n"); in reset_ivb_igd()
3466 pci_iounmap(dev, mmio_base); in reset_ivb_igd()
3473 static int reset_chelsio_generic_dev(struct pci_dev *dev, int probe) in reset_chelsio_generic_dev() argument
3482 if ((dev->device & 0xf000) != 0x4000) in reset_chelsio_generic_dev()
3498 pci_read_config_word(dev, PCI_COMMAND, &old_command); in reset_chelsio_generic_dev()
3499 pci_write_config_word(dev, PCI_COMMAND, in reset_chelsio_generic_dev()
3506 pci_save_state(dev); in reset_chelsio_generic_dev()
3515 pci_read_config_word(dev, dev->msix_cap+PCI_MSIX_FLAGS, &msix_flags); in reset_chelsio_generic_dev()
3517 pci_write_config_word(dev, dev->msix_cap+PCI_MSIX_FLAGS, in reset_chelsio_generic_dev()
3527 if (!pci_wait_for_pending_transaction(dev)) in reset_chelsio_generic_dev()
3528 dev_err(&dev->dev, "transaction is not cleared; proceeding with reset anyway\n"); in reset_chelsio_generic_dev()
3530 pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR); in reset_chelsio_generic_dev()
3542 pci_restore_state(dev); in reset_chelsio_generic_dev()
3543 pci_write_config_word(dev, PCI_COMMAND, old_command); in reset_chelsio_generic_dev()
3570 int pci_dev_specific_reset(struct pci_dev *dev, int probe) in pci_dev_specific_reset() argument
3575 if ((i->vendor == dev->vendor || in pci_dev_specific_reset()
3577 (i->device == dev->device || in pci_dev_specific_reset()
3579 return i->reset(dev, probe); in pci_dev_specific_reset()
3585 static void quirk_dma_func0_alias(struct pci_dev *dev) in quirk_dma_func0_alias() argument
3587 if (PCI_FUNC(dev->devfn) != 0) { in quirk_dma_func0_alias()
3588 dev->dma_alias_devfn = PCI_DEVFN(PCI_SLOT(dev->devfn), 0); in quirk_dma_func0_alias()
3589 dev->dev_flags |= PCI_DEV_FLAGS_DMA_ALIAS_DEVFN; in quirk_dma_func0_alias()
3601 static void quirk_dma_func1_alias(struct pci_dev *dev) in quirk_dma_func1_alias() argument
3603 if (PCI_FUNC(dev->devfn) != 1) { in quirk_dma_func1_alias()
3604 dev->dma_alias_devfn = PCI_DEVFN(PCI_SLOT(dev->devfn), 1); in quirk_dma_func1_alias()
3605 dev->dev_flags |= PCI_DEV_FLAGS_DMA_ALIAS_DEVFN; in quirk_dma_func1_alias()
3661 static void quirk_fixed_dma_alias(struct pci_dev *dev) in quirk_fixed_dma_alias() argument
3665 id = pci_match_id(fixed_dma_alias_tbl, dev); in quirk_fixed_dma_alias()
3667 dev->dma_alias_devfn = id->driver_data; in quirk_fixed_dma_alias()
3668 dev->dev_flags |= PCI_DEV_FLAGS_DMA_ALIAS_DEVFN; in quirk_fixed_dma_alias()
3669 dev_info(&dev->dev, "Enabling fixed DMA alias to %02x.%d\n", in quirk_fixed_dma_alias()
3670 PCI_SLOT(dev->dma_alias_devfn), in quirk_fixed_dma_alias()
3671 PCI_FUNC(dev->dma_alias_devfn)); in quirk_fixed_dma_alias()
3729 static int pci_quirk_amd_sb_acs(struct pci_dev *dev, u16 acs_flags) in pci_quirk_amd_sb_acs() argument
3736 if (!dev->multifunction || !pci_is_root_bus(dev->bus)) in pci_quirk_amd_sb_acs()
3785 static bool pci_quirk_intel_pch_acs_match(struct pci_dev *dev) in pci_quirk_intel_pch_acs_match() argument
3790 if (!pci_is_pcie(dev) || pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT) in pci_quirk_intel_pch_acs_match()
3794 if (pci_quirk_intel_pch_acs_ids[i] == dev->device) in pci_quirk_intel_pch_acs_match()
3802 static int pci_quirk_intel_pch_acs(struct pci_dev *dev, u16 acs_flags) in pci_quirk_intel_pch_acs() argument
3804 u16 flags = dev->dev_flags & PCI_DEV_FLAGS_ACS_ENABLED_QUIRK ? in pci_quirk_intel_pch_acs()
3807 if (!pci_quirk_intel_pch_acs_match(dev)) in pci_quirk_intel_pch_acs()
3813 static int pci_quirk_mf_endpoint_acs(struct pci_dev *dev, u16 acs_flags) in pci_quirk_mf_endpoint_acs() argument
3833 int (*acs_enabled)(struct pci_dev *dev, u16 acs_flags);
3903 int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags) in pci_dev_specific_acs_enabled() argument
3915 if ((i->vendor == dev->vendor || in pci_dev_specific_acs_enabled()
3917 (i->device == dev->device || in pci_dev_specific_acs_enabled()
3919 ret = i->acs_enabled(dev, acs_flags); in pci_dev_specific_acs_enabled()
3947 static int pci_quirk_enable_intel_lpc_acs(struct pci_dev *dev) in pci_quirk_enable_intel_lpc_acs() argument
3957 pci_bus_read_config_dword(dev->bus, PCI_DEVFN(31, 0), in pci_quirk_enable_intel_lpc_acs()
3979 dev_info(&dev->dev, "Disabling UPDCR peer decodes\n"); in pci_quirk_enable_intel_lpc_acs()
3994 static void pci_quirk_enable_intel_rp_mpc_acs(struct pci_dev *dev) in pci_quirk_enable_intel_rp_mpc_acs() argument
4004 pci_read_config_dword(dev, INTEL_MPC_REG, &mpc); in pci_quirk_enable_intel_rp_mpc_acs()
4006 dev_info(&dev->dev, "Enabling MPC IRBNCE\n"); in pci_quirk_enable_intel_rp_mpc_acs()
4008 pci_write_config_word(dev, INTEL_MPC_REG, mpc); in pci_quirk_enable_intel_rp_mpc_acs()
4012 static int pci_quirk_enable_intel_pch_acs(struct pci_dev *dev) in pci_quirk_enable_intel_pch_acs() argument
4014 if (!pci_quirk_intel_pch_acs_match(dev)) in pci_quirk_enable_intel_pch_acs()
4017 if (pci_quirk_enable_intel_lpc_acs(dev)) { in pci_quirk_enable_intel_pch_acs()
4018 dev_warn(&dev->dev, "Failed to enable Intel PCH ACS quirk\n"); in pci_quirk_enable_intel_pch_acs()
4022 pci_quirk_enable_intel_rp_mpc_acs(dev); in pci_quirk_enable_intel_pch_acs()
4024 dev->dev_flags |= PCI_DEV_FLAGS_ACS_ENABLED_QUIRK; in pci_quirk_enable_intel_pch_acs()
4026 dev_info(&dev->dev, "Intel PCH root port ACS workaround enabled\n"); in pci_quirk_enable_intel_pch_acs()
4034 int (*enable_acs)(struct pci_dev *dev);
4040 void pci_dev_specific_enable_acs(struct pci_dev *dev) in pci_dev_specific_enable_acs() argument
4046 if ((i->vendor == dev->vendor || in pci_dev_specific_enable_acs()
4048 (i->device == dev->device || in pci_dev_specific_enable_acs()
4050 ret = i->enable_acs(dev); in pci_dev_specific_enable_acs()