68 	u32 val, data[2];  in hix5hd2_sata_phy_init()  local
85 	val = readl_relaxed(priv->base + SATA_PHY0_CTLL);  in hix5hd2_sata_phy_init()
86 	val &= ~(MPLL_MULTIPLIER_MASK | REF_USE_PAD);  in hix5hd2_sata_phy_init()
87 	val |= MPLL_MULTIPLIER_50M << MPLL_MULTIPLIER_SHIFT |  in hix5hd2_sata_phy_init()
89 	writel_relaxed(val, priv->base + SATA_PHY0_CTLL);  in hix5hd2_sata_phy_init()
91 	val &= ~PHY_RESET;  in hix5hd2_sata_phy_init()
92 	writel_relaxed(val, priv->base + SATA_PHY0_CTLL);  in hix5hd2_sata_phy_init()
94 	val = readl_relaxed(priv->base + SATA_PORT_PHYCTL1);  in hix5hd2_sata_phy_init()
95 	val &= ~AMPLITUDE_MASK;  in hix5hd2_sata_phy_init()
96 	val |= AMPLITUDE_GEN3 << AMPLITUDE_GEN3_SHIFT |  in hix5hd2_sata_phy_init()
99 	writel_relaxed(val, priv->base + SATA_PORT_PHYCTL1);  in hix5hd2_sata_phy_init()
101 	val = readl_relaxed(priv->base + SATA_PORT_PHYCTL2);  in hix5hd2_sata_phy_init()
102 	val &= ~PREEMPH_MASK;  in hix5hd2_sata_phy_init()
103 	val |= PREEMPH_GEN3 << PREEMPH_GEN3_SHIFT |  in hix5hd2_sata_phy_init()
106 	writel_relaxed(val, priv->base + SATA_PORT_PHYCTL2);  in hix5hd2_sata_phy_init()
109 	val = readl_relaxed(priv->base + SATA_PORT_PHYCTL);  in hix5hd2_sata_phy_init()
110 	val &= ~SPEED_MODE_MASK;  in hix5hd2_sata_phy_init()
111 	val |= SPEED_MODE_GEN1 << HALF_RATE_SHIFT |  in hix5hd2_sata_phy_init()
114 	writel_relaxed(val, priv->base + SATA_PORT_PHYCTL);  in hix5hd2_sata_phy_init()
117 	val &= ~SPEED_MODE_MASK;  in hix5hd2_sata_phy_init()
118 	val |= SPEED_MODE_GEN3 << HALF_RATE_SHIFT |  in hix5hd2_sata_phy_init()
121 	writel_relaxed(val, priv->base + SATA_PORT_PHYCTL);  in hix5hd2_sata_phy_init()
123 	val &= ~(SPEED_MODE_MASK | SPEED_CTRL);  in hix5hd2_sata_phy_init()
124 	val |= SPEED_MODE_GEN2 << HALF_RATE_SHIFT |  in hix5hd2_sata_phy_init()
127 	writel_relaxed(val, priv->base + SATA_PORT_PHYCTL);  in hix5hd2_sata_phy_init()