177 static int miphy365x_set_path(struct miphy365x_phy *miphy_phy,  in miphy365x_set_path()  argument
180 	bool sata = (miphy_phy->type == PHY_TYPE_SATA);  in miphy365x_set_path()
183 				  miphy_phy->ctrlreg,  in miphy365x_set_path()
188 static int miphy365x_init_pcie_port(struct miphy365x_phy *miphy_phy,  in miphy365x_init_pcie_port()  argument
193 	if (miphy_phy->pcie_tx_pol_inv) {  in miphy365x_init_pcie_port()
196 		writeb_relaxed(val, miphy_phy->base + CTRL_REG);  in miphy365x_init_pcie_port()
197 		writeb_relaxed(0x00, miphy_phy->base + PCIE_REG);  in miphy365x_init_pcie_port()
203 static inline int miphy365x_hfc_not_rdy(struct miphy365x_phy *miphy_phy,  in miphy365x_hfc_not_rdy()  argument
211 		regval = readb_relaxed(miphy_phy->base + STATUS_REG);  in miphy365x_hfc_not_rdy()
222 static inline int miphy365x_rdy(struct miphy365x_phy *miphy_phy,  in miphy365x_rdy()  argument
230 		regval = readb_relaxed(miphy_phy->base + STATUS_REG);  in miphy365x_rdy()
241 static inline void miphy365x_set_comp(struct miphy365x_phy *miphy_phy,  in miphy365x_set_comp()  argument
246 	if (miphy_phy->sata_gen == SATA_GEN1)  in miphy365x_set_comp()
248 			       miphy_phy->base + COMP_CTRL2_REG);  in miphy365x_set_comp()
251 			       miphy_phy->base + COMP_CTRL2_REG);  in miphy365x_set_comp()
253 	if (miphy_phy->sata_gen != SATA_GEN3) {  in miphy365x_set_comp()
255 			       miphy_phy->base + COMP_CTRL3_REG);  in miphy365x_set_comp()
261 		writeb_relaxed(BYPASS_PLL_CAL, miphy_phy->base + PLL_CTRL2_REG);  in miphy365x_set_comp()
262 		writeb_relaxed(COMZC_IDLL, miphy_phy->base + COMP_IDLL_REG);  in miphy365x_set_comp()
270 	writeb_relaxed(val, miphy_phy->base + COMP_CTRL1_REG);  in miphy365x_set_comp()
273 	while ((readb_relaxed(miphy_phy->base + COMP_CTRL1_REG) & mask)	!= mask)  in miphy365x_set_comp()
277 static inline void miphy365x_set_ssc(struct miphy365x_phy *miphy_phy,  in miphy365x_set_ssc()  argument
288 		       miphy_phy->base + PLL_SSC_STEP_MSB_REG);  in miphy365x_set_ssc()
290 		       miphy_phy->base + PLL_SSC_STEP_LSB_REG);  in miphy365x_set_ssc()
292 		       miphy_phy->base + PLL_SSC_PER_MSB_REG);  in miphy365x_set_ssc()
294 		       miphy_phy->base + PLL_SSC_PER_LSB_REG);  in miphy365x_set_ssc()
297 	if (miphy_phy->sata_gen == SATA_GEN1) {  in miphy365x_set_ssc()
299 		writeb_relaxed(val, miphy_phy->base + PLL_CTRL1_REG);  in miphy365x_set_ssc()
302 		writeb_relaxed(val, miphy_phy->base + PLL_CTRL1_REG);  in miphy365x_set_ssc()
306 static int miphy365x_init_sata_port(struct miphy365x_phy *miphy_phy,  in miphy365x_init_sata_port()  argument
317 	writeb_relaxed(val, miphy_phy->base + RESET_REG);  in miphy365x_init_sata_port()
319 	if (miphy_phy->sata_tx_pol_inv)  in miphy365x_init_sata_port()
320 		writeb_relaxed(TX_POL, miphy_phy->base + CTRL_REG);  in miphy365x_init_sata_port()
327 	writeb_relaxed(SPDSEL_SEL, miphy_phy->base + BOUNDARY1_REG);  in miphy365x_init_sata_port()
328 	writeb_relaxed(START_CLK_HF, miphy_phy->base + IDLL_TEST_REG);  in miphy365x_init_sata_port()
329 	val = rx_tx_spd[miphy_phy->sata_gen];  in miphy365x_init_sata_port()
330 	writeb_relaxed(val, miphy_phy->base + BOUNDARY3_REG);  in miphy365x_init_sata_port()
333 	ret = miphy365x_hfc_not_rdy(miphy_phy, miphy_dev);  in miphy365x_init_sata_port()
338 	miphy365x_set_comp(miphy_phy, miphy_dev);  in miphy365x_init_sata_port()
340 	switch (miphy_phy->sata_gen) {  in miphy365x_init_sata_port()
348 		writeb_relaxed(val, miphy_phy->base + BUF_SEL_REG);  in miphy365x_init_sata_port()
350 		writeb_relaxed(val, miphy_phy->base + TXBUF1_REG);  in miphy365x_init_sata_port()
351 		writeb_relaxed(TXSLEW_VAL, miphy_phy->base + TXBUF2_REG);  in miphy365x_init_sata_port()
352 		writeb_relaxed(0x00, miphy_phy->base + RXBUF_OFFSET_CTRL_REG);  in miphy365x_init_sata_port()
354 		writeb_relaxed(val, miphy_phy->base + RXBUF_REG);  in miphy365x_init_sata_port()
365 			       miphy_phy->base + BUF_SEL_REG);  in miphy365x_init_sata_port()
366 		writeb_relaxed(SWING_VAL, miphy_phy->base + TXBUF1_REG);  in miphy365x_init_sata_port()
367 		writeb_relaxed(TXSLEW_VAL, miphy_phy->base + TXBUF2_REG);  in miphy365x_init_sata_port()
369 		writeb_relaxed(val, miphy_phy->base + RXBUF_REG);  in miphy365x_init_sata_port()
378 		writeb_relaxed(PD_VDDTFILTER, miphy_phy->base + BUF_SEL_REG);  in miphy365x_init_sata_port()
379 		writeb_relaxed(SWING_VAL_GEN1, miphy_phy->base + TXBUF1_REG);  in miphy365x_init_sata_port()
380 		writeb_relaxed(TXSLEW_VAL_GEN1,	miphy_phy->base + TXBUF2_REG);  in miphy365x_init_sata_port()
387 	writeb_relaxed(RST_RX, miphy_phy->base + RESET_REG);  in miphy365x_init_sata_port()
390 	miphy365x_set_ssc(miphy_phy, miphy_dev);  in miphy365x_init_sata_port()
393 	ret = miphy365x_rdy(miphy_phy, miphy_dev);  in miphy365x_init_sata_port()
405 	writeb_relaxed(0x00, miphy_phy->base + BOUNDARY1_REG);  in miphy365x_init_sata_port()
406 	writeb_relaxed(0x00, miphy_phy->base + IDLL_TEST_REG);  in miphy365x_init_sata_port()
407 	writeb_relaxed(RST_RX, miphy_phy->base + RESET_REG);  in miphy365x_init_sata_port()
408 	val = miphy_phy->sata_tx_pol_inv ?  in miphy365x_init_sata_port()
410 	writeb_relaxed(val, miphy_phy->base + CTRL_REG);  in miphy365x_init_sata_port()
413 	writeb_relaxed(val, miphy_phy->base + DES_BITLOCK_REG);  in miphy365x_init_sata_port()
414 	writeb_relaxed(0x00, miphy_phy->base + RESET_REG);  in miphy365x_init_sata_port()
421 	struct miphy365x_phy *miphy_phy = phy_get_drvdata(phy);  in miphy365x_init()  local
427 	ret = miphy365x_set_path(miphy_phy, miphy_dev);  in miphy365x_init()
434 	if (miphy_phy->type == PHY_TYPE_PCIE)  in miphy365x_init()
435 		ret = miphy365x_init_pcie_port(miphy_phy, miphy_dev);  in miphy365x_init()
437 		ret = miphy365x_init_sata_port(miphy_phy, miphy_dev);  in miphy365x_init()
444 int miphy365x_get_addr(struct device *dev, struct miphy365x_phy *miphy_phy,  in miphy365x_get_addr()  argument
447 	struct device_node *phynode = miphy_phy->phy->dev.of_node;  in miphy365x_get_addr()
449 	int type = miphy_phy->type;  in miphy365x_get_addr()
462 	miphy_phy->base = of_iomap(phynode, index);  in miphy365x_get_addr()
463 	if (!miphy_phy->base) {  in miphy365x_get_addr()
475 	struct miphy365x_phy *miphy_phy = NULL;  in miphy365x_xlate()  local
491 			miphy_phy = miphy_dev->phys[index];  in miphy365x_xlate()
495 	if (!miphy_phy) {  in miphy365x_xlate()
500 	miphy_phy->type = args->args[0];  in miphy365x_xlate()
502 	if (!(miphy_phy->type == PHY_TYPE_SATA ||  in miphy365x_xlate()
503 	      miphy_phy->type == PHY_TYPE_PCIE)) {  in miphy365x_xlate()
504 		dev_err(dev, "Unsupported device type: %d\n", miphy_phy->type);  in miphy365x_xlate()
510 		ret = miphy365x_get_addr(dev, miphy_phy, index);  in miphy365x_xlate()
515 	return miphy_phy->phy;  in miphy365x_xlate()
524 			      struct miphy365x_phy *miphy_phy)  in miphy365x_of_probe()  argument
526 	of_property_read_u32(phynode, "st,sata-gen", &miphy_phy->sata_gen);  in miphy365x_of_probe()
527 	if (!miphy_phy->sata_gen)  in miphy365x_of_probe()
528 		miphy_phy->sata_gen = SATA_GEN1;  in miphy365x_of_probe()
530 	miphy_phy->pcie_tx_pol_inv =  in miphy365x_of_probe()
533 	miphy_phy->sata_tx_pol_inv =  in miphy365x_of_probe()
570 		struct miphy365x_phy *miphy_phy;  in miphy365x_probe()  local
572 		miphy_phy = devm_kzalloc(&pdev->dev, sizeof(*miphy_phy),  in miphy365x_probe()
574 		if (!miphy_phy)  in miphy365x_probe()
577 		miphy_dev->phys[port] = miphy_phy;  in miphy365x_probe()
587 		ret = miphy365x_of_probe(child, miphy_phy);  in miphy365x_probe()
596 					&miphy_phy->ctrlreg);  in miphy365x_probe()