566 	u32 val;  in sds_wr()  local
576 		val = readl(csr_base + indirect_cmd_reg);  in sds_wr()
577 	} while (!(val & CFG_IND_CMD_DONE_MASK) &&  in sds_wr()
579 	if (!(val & CFG_IND_CMD_DONE_MASK))  in sds_wr()
588 	u32 val;  in sds_rd()  local
596 		val = readl(csr_base + indirect_cmd_reg);  in sds_rd()
597 	} while (!(val & CFG_IND_CMD_DONE_MASK) &&  in sds_rd()
600 	if (!(val & CFG_IND_CMD_DONE_MASK))  in sds_rd()
609 	u32 val;  in cmu_wr()  local
618 		SATA_ENET_SDS_IND_RDATA_REG, reg, &val);  in cmu_wr()
619 	pr_debug("CMU WR addr 0x%X value 0x%08X <-> 0x%08X\n", reg, data, val);  in cmu_wr()
639 	u32 val;  in cmu_toggle1to0()  local
641 	cmu_rd(ctx, cmu_type, reg, &val);  in cmu_toggle1to0()
642 	val |= bits;  in cmu_toggle1to0()
643 	cmu_wr(ctx, cmu_type, reg, val);  in cmu_toggle1to0()
644 	cmu_rd(ctx, cmu_type, reg, &val);  in cmu_toggle1to0()
645 	val &= ~bits;  in cmu_toggle1to0()
646 	cmu_wr(ctx, cmu_type, reg, val);  in cmu_toggle1to0()
652 	u32 val;  in cmu_clrbits()  local
654 	cmu_rd(ctx, cmu_type, reg, &val);  in cmu_clrbits()
655 	val &= ~bits;  in cmu_clrbits()
656 	cmu_wr(ctx, cmu_type, reg, val);  in cmu_clrbits()
662 	u32 val;  in cmu_setbits()  local
664 	cmu_rd(ctx, cmu_type, reg, &val);  in cmu_setbits()
665 	val |= bits;  in cmu_setbits()
666 	cmu_wr(ctx, cmu_type, reg, val);  in cmu_setbits()
672 	u32 val;  in serdes_wr()  local
679 	       SATA_ENET_SDS_IND_RDATA_REG, reg, &val);  in serdes_wr()
681 		 val);  in serdes_wr()
698 	u32 val;  in serdes_clrbits()  local
700 	serdes_rd(ctx, lane, reg, &val);  in serdes_clrbits()
701 	val &= ~bits;  in serdes_clrbits()
702 	serdes_wr(ctx, lane, reg, val);  in serdes_clrbits()
708 	u32 val;  in serdes_setbits()  local
710 	serdes_rd(ctx, lane, reg, &val);  in serdes_setbits()
711 	val |= bits;  in serdes_setbits()
712 	serdes_wr(ctx, lane, reg, val);  in serdes_setbits()
719 	u32 val;  in xgene_phy_cfg_cmu_clk_type()  local
722 	cmu_rd(ctx, cmu_type, CMU_REG12, &val);  in xgene_phy_cfg_cmu_clk_type()
723 	val = CMU_REG12_STATE_DELAY9_SET(val, 0x1);  in xgene_phy_cfg_cmu_clk_type()
724 	cmu_wr(ctx, cmu_type, CMU_REG12, val);  in xgene_phy_cfg_cmu_clk_type()
732 		cmu_rd(ctx, cmu_type, CMU_REG0, &val);  in xgene_phy_cfg_cmu_clk_type()
733 		val = CMU_REG0_PLL_REF_SEL_SET(val, 0x0);  in xgene_phy_cfg_cmu_clk_type()
734 		cmu_wr(ctx, cmu_type, CMU_REG0, val);  in xgene_phy_cfg_cmu_clk_type()
736 		cmu_rd(ctx, cmu_type, CMU_REG1, &val);  in xgene_phy_cfg_cmu_clk_type()
737 		val = CMU_REG1_REFCLK_CMOS_SEL_SET(val, 0x0);  in xgene_phy_cfg_cmu_clk_type()
738 		cmu_wr(ctx, cmu_type, CMU_REG1, val);  in xgene_phy_cfg_cmu_clk_type()
742 		cmu_rd(ctx, cmu_type, CMU_REG0, &val);  in xgene_phy_cfg_cmu_clk_type()
743 		val = CMU_REG0_PLL_REF_SEL_SET(val, 0x1);  in xgene_phy_cfg_cmu_clk_type()
744 		cmu_wr(ctx, cmu_type, CMU_REG0, val);  in xgene_phy_cfg_cmu_clk_type()
746 		cmu_rd(ctx, cmu_type, CMU_REG1, &val);  in xgene_phy_cfg_cmu_clk_type()
747 		val = CMU_REG1_REFCLK_CMOS_SEL_SET(val, 0x1);  in xgene_phy_cfg_cmu_clk_type()
748 		cmu_wr(ctx, cmu_type, CMU_REG1, val);  in xgene_phy_cfg_cmu_clk_type()
757 		cmu_rd(ctx, cmu_type, CMU_REG1, &val);  in xgene_phy_cfg_cmu_clk_type()
758 		val = CMU_REG1_REFCLK_CMOS_SEL_SET(val, 0x1);  in xgene_phy_cfg_cmu_clk_type()
759 		cmu_wr(ctx, cmu_type, CMU_REG1, val);  in xgene_phy_cfg_cmu_clk_type()
761 		cmu_rd(ctx, cmu_type, CMU_REG1, &val);  in xgene_phy_cfg_cmu_clk_type()
762 		val = CMU_REG1_REFCLK_CMOS_SEL_SET(val, 0x0);  in xgene_phy_cfg_cmu_clk_type()
763 		cmu_wr(ctx, cmu_type, CMU_REG1, val);  in xgene_phy_cfg_cmu_clk_type()
773 	u32 val;  in xgene_phy_sata_cfg_cmu_core()  local
778 		cmu_rd(ctx, cmu_type, CMU_REG34, &val);  in xgene_phy_sata_cfg_cmu_core()
779 		val = CMU_REG34_VCO_CAL_VTH_LO_MAX_SET(val, 0x7);  in xgene_phy_sata_cfg_cmu_core()
780 		val = CMU_REG34_VCO_CAL_VTH_HI_MAX_SET(val, 0xc);  in xgene_phy_sata_cfg_cmu_core()
781 		val = CMU_REG34_VCO_CAL_VTH_LO_MIN_SET(val, 0x3);  in xgene_phy_sata_cfg_cmu_core()
782 		val = CMU_REG34_VCO_CAL_VTH_HI_MIN_SET(val, 0x8);  in xgene_phy_sata_cfg_cmu_core()
783 		cmu_wr(ctx, cmu_type, CMU_REG34, val);  in xgene_phy_sata_cfg_cmu_core()
787 	cmu_rd(ctx, cmu_type, CMU_REG0, &val);  in xgene_phy_sata_cfg_cmu_core()
789 		val = CMU_REG0_CAL_COUNT_RESOL_SET(val, 0x4);  in xgene_phy_sata_cfg_cmu_core()
791 		val = CMU_REG0_CAL_COUNT_RESOL_SET(val, 0x7);  in xgene_phy_sata_cfg_cmu_core()
792 	cmu_wr(ctx, cmu_type, CMU_REG0, val);  in xgene_phy_sata_cfg_cmu_core()
795 	cmu_rd(ctx, cmu_type, CMU_REG1, &val);  in xgene_phy_sata_cfg_cmu_core()
796 	val = CMU_REG1_PLL_CP_SET(val, 0x1);  in xgene_phy_sata_cfg_cmu_core()
798 		val = CMU_REG1_PLL_CP_SEL_SET(val, 0x5);  in xgene_phy_sata_cfg_cmu_core()
800 		val = CMU_REG1_PLL_CP_SEL_SET(val, 0x3);  in xgene_phy_sata_cfg_cmu_core()
802 		val = CMU_REG1_PLL_MANUALCAL_SET(val, 0x0);  in xgene_phy_sata_cfg_cmu_core()
804 		val = CMU_REG1_PLL_MANUALCAL_SET(val, 0x1);  in xgene_phy_sata_cfg_cmu_core()
805 	cmu_wr(ctx, cmu_type, CMU_REG1, val);  in xgene_phy_sata_cfg_cmu_core()
811 	cmu_rd(ctx, cmu_type, CMU_REG2, &val);  in xgene_phy_sata_cfg_cmu_core()
813 		val = CMU_REG2_PLL_LFRES_SET(val, 0xa);  in xgene_phy_sata_cfg_cmu_core()
816 		val = CMU_REG2_PLL_LFRES_SET(val, 0x3);  in xgene_phy_sata_cfg_cmu_core()
823 		val = CMU_REG2_PLL_FBDIV_SET(val, FBDIV_VAL_100M);  in xgene_phy_sata_cfg_cmu_core()
824 		val = CMU_REG2_PLL_REFDIV_SET(val, REFDIV_VAL_100M);  in xgene_phy_sata_cfg_cmu_core()
826 		val = CMU_REG2_PLL_FBDIV_SET(val, FBDIV_VAL_50M);  in xgene_phy_sata_cfg_cmu_core()
827 		val = CMU_REG2_PLL_REFDIV_SET(val, REFDIV_VAL_50M);  in xgene_phy_sata_cfg_cmu_core()
829 	cmu_wr(ctx, cmu_type, CMU_REG2, val);  in xgene_phy_sata_cfg_cmu_core()
832 	cmu_rd(ctx, cmu_type, CMU_REG3, &val);  in xgene_phy_sata_cfg_cmu_core()
834 		val = CMU_REG3_VCOVARSEL_SET(val, 0x3);  in xgene_phy_sata_cfg_cmu_core()
835 		val = CMU_REG3_VCO_MOMSEL_INIT_SET(val, 0x10);  in xgene_phy_sata_cfg_cmu_core()
837 		val = CMU_REG3_VCOVARSEL_SET(val, 0xF);  in xgene_phy_sata_cfg_cmu_core()
839 			val = CMU_REG3_VCO_MOMSEL_INIT_SET(val, 0x15);  in xgene_phy_sata_cfg_cmu_core()
841 			val = CMU_REG3_VCO_MOMSEL_INIT_SET(val, 0x1a);  in xgene_phy_sata_cfg_cmu_core()
842 		val = CMU_REG3_VCO_MANMOMSEL_SET(val, 0x15);  in xgene_phy_sata_cfg_cmu_core()
844 	cmu_wr(ctx, cmu_type, CMU_REG3, val);  in xgene_phy_sata_cfg_cmu_core()
847 	cmu_rd(ctx, cmu_type, CMU_REG26, &val);  in xgene_phy_sata_cfg_cmu_core()
848 	val = CMU_REG26_FORCE_PLL_LOCK_SET(val, 0x0);  in xgene_phy_sata_cfg_cmu_core()
849 	cmu_wr(ctx, cmu_type, CMU_REG26, val);  in xgene_phy_sata_cfg_cmu_core()
852 	cmu_rd(ctx, cmu_type, CMU_REG5, &val);  in xgene_phy_sata_cfg_cmu_core()
853 	val = CMU_REG5_PLL_LFSMCAP_SET(val, 0x3);  in xgene_phy_sata_cfg_cmu_core()
854 	val = CMU_REG5_PLL_LFCAP_SET(val, 0x3);  in xgene_phy_sata_cfg_cmu_core()
856 		val = CMU_REG5_PLL_LOCK_RESOLUTION_SET(val, 0x7);  in xgene_phy_sata_cfg_cmu_core()
858 		val = CMU_REG5_PLL_LOCK_RESOLUTION_SET(val, 0x4);  in xgene_phy_sata_cfg_cmu_core()
859 	cmu_wr(ctx, cmu_type, CMU_REG5, val);  in xgene_phy_sata_cfg_cmu_core()
862 	cmu_rd(ctx, cmu_type, CMU_REG6, &val);  in xgene_phy_sata_cfg_cmu_core()
863 	val = CMU_REG6_PLL_VREGTRIM_SET(val, preA3Chip ? 0x0 : 0x2);  in xgene_phy_sata_cfg_cmu_core()
864 	val = CMU_REG6_MAN_PVT_CAL_SET(val, preA3Chip ? 0x1 : 0x0);  in xgene_phy_sata_cfg_cmu_core()
865 	cmu_wr(ctx, cmu_type, CMU_REG6, val);  in xgene_phy_sata_cfg_cmu_core()
869 		cmu_rd(ctx, cmu_type, CMU_REG9, &val);  in xgene_phy_sata_cfg_cmu_core()
870 		val = CMU_REG9_TX_WORD_MODE_CH1_SET(val,  in xgene_phy_sata_cfg_cmu_core()
872 		val = CMU_REG9_TX_WORD_MODE_CH0_SET(val,  in xgene_phy_sata_cfg_cmu_core()
874 		val = CMU_REG9_PLL_POST_DIVBY2_SET(val, 0x1);  in xgene_phy_sata_cfg_cmu_core()
876 			val = CMU_REG9_VBG_BYPASSB_SET(val, 0x0);  in xgene_phy_sata_cfg_cmu_core()
877 			val = CMU_REG9_IGEN_BYPASS_SET(val , 0x0);  in xgene_phy_sata_cfg_cmu_core()
879 		cmu_wr(ctx, cmu_type, CMU_REG9, val);  in xgene_phy_sata_cfg_cmu_core()
882 			cmu_rd(ctx, cmu_type, CMU_REG10, &val);  in xgene_phy_sata_cfg_cmu_core()
883 			val = CMU_REG10_VREG_REFSEL_SET(val, 0x1);  in xgene_phy_sata_cfg_cmu_core()
884 			cmu_wr(ctx, cmu_type, CMU_REG10, val);  in xgene_phy_sata_cfg_cmu_core()
888 	cmu_rd(ctx, cmu_type, CMU_REG16, &val);  in xgene_phy_sata_cfg_cmu_core()
889 	val = CMU_REG16_CALIBRATION_DONE_OVERRIDE_SET(val, 0x1);  in xgene_phy_sata_cfg_cmu_core()
890 	val = CMU_REG16_BYPASS_PLL_LOCK_SET(val, 0x1);  in xgene_phy_sata_cfg_cmu_core()
892 		val = CMU_REG16_VCOCAL_WAIT_BTW_CODE_SET(val, 0x4);  in xgene_phy_sata_cfg_cmu_core()
894 		val = CMU_REG16_VCOCAL_WAIT_BTW_CODE_SET(val, 0x7);  in xgene_phy_sata_cfg_cmu_core()
895 	cmu_wr(ctx, cmu_type, CMU_REG16, val);  in xgene_phy_sata_cfg_cmu_core()
898 	cmu_rd(ctx, cmu_type, CMU_REG30, &val);  in xgene_phy_sata_cfg_cmu_core()
899 	val = CMU_REG30_PCIE_MODE_SET(val, 0x0);  in xgene_phy_sata_cfg_cmu_core()
900 	val = CMU_REG30_LOCK_COUNT_SET(val, 0x3);  in xgene_phy_sata_cfg_cmu_core()
901 	cmu_wr(ctx, cmu_type, CMU_REG30, val);  in xgene_phy_sata_cfg_cmu_core()
906 	cmu_rd(ctx, cmu_type, CMU_REG32, &val);  in xgene_phy_sata_cfg_cmu_core()
907 	val = CMU_REG32_PVT_CAL_WAIT_SEL_SET(val, 0x3);  in xgene_phy_sata_cfg_cmu_core()
909 		val = CMU_REG32_IREF_ADJ_SET(val, 0x3);  in xgene_phy_sata_cfg_cmu_core()
911 		val = CMU_REG32_IREF_ADJ_SET(val, 0x1);  in xgene_phy_sata_cfg_cmu_core()
912 	cmu_wr(ctx, cmu_type, CMU_REG32, val);  in xgene_phy_sata_cfg_cmu_core()
927 	u32 val;  in xgene_phy_ssc_enable()  local
930 	cmu_rd(ctx, cmu_type, CMU_REG35, &val);  in xgene_phy_ssc_enable()
931 	val = CMU_REG35_PLL_SSC_MOD_SET(val, 98);  in xgene_phy_ssc_enable()
932 	cmu_wr(ctx, cmu_type, CMU_REG35, val);  in xgene_phy_ssc_enable()
935 	cmu_rd(ctx, cmu_type, CMU_REG36, &val);  in xgene_phy_ssc_enable()
936 	val = CMU_REG36_PLL_SSC_VSTEP_SET(val, 30);  in xgene_phy_ssc_enable()
937 	val = CMU_REG36_PLL_SSC_EN_SET(val, 1);  in xgene_phy_ssc_enable()
938 	val = CMU_REG36_PLL_SSC_DSMSEL_SET(val, 1);  in xgene_phy_ssc_enable()
939 	cmu_wr(ctx, cmu_type, CMU_REG36, val);  in xgene_phy_ssc_enable()
952 	u32 val;  in xgene_phy_sata_cfg_lanes()  local
961 		serdes_rd(ctx, lane, RXTX_REG0, &val);  in xgene_phy_sata_cfg_lanes()
962 		val = RXTX_REG0_CTLE_EQ_HR_SET(val, 0x10);  in xgene_phy_sata_cfg_lanes()
963 		val = RXTX_REG0_CTLE_EQ_QR_SET(val, 0x10);  in xgene_phy_sata_cfg_lanes()
964 		val = RXTX_REG0_CTLE_EQ_FR_SET(val, 0x10);  in xgene_phy_sata_cfg_lanes()
965 		serdes_wr(ctx, lane, RXTX_REG0, val);  in xgene_phy_sata_cfg_lanes()
968 		serdes_rd(ctx, lane, RXTX_REG1, &val);  in xgene_phy_sata_cfg_lanes()
969 		val = RXTX_REG1_RXACVCM_SET(val, 0x7);  in xgene_phy_sata_cfg_lanes()
970 		val = RXTX_REG1_CTLE_EQ_SET(val,  in xgene_phy_sata_cfg_lanes()
973 		serdes_wr(ctx, lane, RXTX_REG1, val);  in xgene_phy_sata_cfg_lanes()
977 		serdes_rd(ctx, lane, RXTX_REG2, &val);  in xgene_phy_sata_cfg_lanes()
978 		val = RXTX_REG2_VTT_ENA_SET(val, 0x1);  in xgene_phy_sata_cfg_lanes()
979 		val = RXTX_REG2_VTT_SEL_SET(val, 0x1);  in xgene_phy_sata_cfg_lanes()
980 		val = RXTX_REG2_TX_FIFO_ENA_SET(val, 0x1);  in xgene_phy_sata_cfg_lanes()
981 		serdes_wr(ctx, lane, RXTX_REG2, val);  in xgene_phy_sata_cfg_lanes()
984 		serdes_rd(ctx, lane, RXTX_REG4, &val);  in xgene_phy_sata_cfg_lanes()
985 		val = RXTX_REG4_TX_WORD_MODE_SET(val, CMU_REG9_WORD_LEN_20BIT);  in xgene_phy_sata_cfg_lanes()
986 		serdes_wr(ctx, lane, RXTX_REG4, val);  in xgene_phy_sata_cfg_lanes()
989 			serdes_rd(ctx, lane, RXTX_REG1, &val);  in xgene_phy_sata_cfg_lanes()
990 			val = RXTX_REG1_RXVREG1_SET(val, 0x2);  in xgene_phy_sata_cfg_lanes()
991 			val = RXTX_REG1_RXIREF_ADJ_SET(val, 0x2);  in xgene_phy_sata_cfg_lanes()
992 			serdes_wr(ctx, lane, RXTX_REG1, val);  in xgene_phy_sata_cfg_lanes()
996 		serdes_rd(ctx, lane, RXTX_REG5, &val);  in xgene_phy_sata_cfg_lanes()
997 		val = RXTX_REG5_TX_CN1_SET(val,  in xgene_phy_sata_cfg_lanes()
1000 		val = RXTX_REG5_TX_CP1_SET(val,  in xgene_phy_sata_cfg_lanes()
1003 		val = RXTX_REG5_TX_CN2_SET(val,  in xgene_phy_sata_cfg_lanes()
1006 		serdes_wr(ctx, lane, RXTX_REG5, val);  in xgene_phy_sata_cfg_lanes()
1009 		serdes_rd(ctx, lane, RXTX_REG6, &val);  in xgene_phy_sata_cfg_lanes()
1010 		val = RXTX_REG6_TXAMP_CNTL_SET(val,  in xgene_phy_sata_cfg_lanes()
1013 		val = RXTX_REG6_TXAMP_ENA_SET(val, 0x1);  in xgene_phy_sata_cfg_lanes()
1014 		val = RXTX_REG6_TX_IDLE_SET(val, 0x0);  in xgene_phy_sata_cfg_lanes()
1015 		val = RXTX_REG6_RX_BIST_RESYNC_SET(val, 0x0);  in xgene_phy_sata_cfg_lanes()
1016 		val = RXTX_REG6_RX_BIST_ERRCNT_RD_SET(val, 0x0);  in xgene_phy_sata_cfg_lanes()
1017 		serdes_wr(ctx, lane, RXTX_REG6, val);  in xgene_phy_sata_cfg_lanes()
1020 		serdes_rd(ctx, lane, RXTX_REG7, &val);  in xgene_phy_sata_cfg_lanes()
1021 		val = RXTX_REG7_BIST_ENA_RX_SET(val, 0x0);  in xgene_phy_sata_cfg_lanes()
1022 		val = RXTX_REG7_RX_WORD_MODE_SET(val, CMU_REG9_WORD_LEN_20BIT);  in xgene_phy_sata_cfg_lanes()
1023 		serdes_wr(ctx, lane, RXTX_REG7, val);  in xgene_phy_sata_cfg_lanes()
1026 		serdes_rd(ctx, lane, RXTX_REG8, &val);  in xgene_phy_sata_cfg_lanes()
1027 		val = RXTX_REG8_CDR_LOOP_ENA_SET(val, 0x1);  in xgene_phy_sata_cfg_lanes()
1028 		val = RXTX_REG8_CDR_BYPASS_RXLOS_SET(val, 0x0);  in xgene_phy_sata_cfg_lanes()
1029 		val = RXTX_REG8_SSC_ENABLE_SET(val, 0x1);  in xgene_phy_sata_cfg_lanes()
1030 		val = RXTX_REG8_SD_DISABLE_SET(val, 0x0);  in xgene_phy_sata_cfg_lanes()
1031 		val = RXTX_REG8_SD_VREF_SET(val, 0x4);  in xgene_phy_sata_cfg_lanes()
1032 		serdes_wr(ctx, lane, RXTX_REG8, val);  in xgene_phy_sata_cfg_lanes()
1035 		serdes_rd(ctx, lane, RXTX_REG11, &val);  in xgene_phy_sata_cfg_lanes()
1036 		val = RXTX_REG11_PHASE_ADJUST_LIMIT_SET(val, 0x0);  in xgene_phy_sata_cfg_lanes()
1037 		serdes_wr(ctx, lane, RXTX_REG11, val);  in xgene_phy_sata_cfg_lanes()
1040 		serdes_rd(ctx, lane, RXTX_REG12, &val);  in xgene_phy_sata_cfg_lanes()
1041 		val = RXTX_REG12_LATCH_OFF_ENA_SET(val, 0x1);  in xgene_phy_sata_cfg_lanes()
1042 		val = RXTX_REG12_SUMOS_ENABLE_SET(val, 0x0);  in xgene_phy_sata_cfg_lanes()
1043 		val = RXTX_REG12_RX_DET_TERM_ENABLE_SET(val, 0x0);  in xgene_phy_sata_cfg_lanes()
1044 		serdes_wr(ctx, lane, RXTX_REG12, val);  in xgene_phy_sata_cfg_lanes()
1047 		serdes_rd(ctx, lane, RXTX_REG26, &val);  in xgene_phy_sata_cfg_lanes()
1048 		val = RXTX_REG26_PERIOD_ERROR_LATCH_SET(val, 0x0);  in xgene_phy_sata_cfg_lanes()
1049 		val = RXTX_REG26_BLWC_ENA_SET(val, 0x1);  in xgene_phy_sata_cfg_lanes()
1050 		serdes_wr(ctx, lane, RXTX_REG26, val);  in xgene_phy_sata_cfg_lanes()
1058 		serdes_rd(ctx, lane, RXTX_REG61, &val);  in xgene_phy_sata_cfg_lanes()
1059 		val = RXTX_REG61_ISCAN_INBERT_SET(val, 0x1);  in xgene_phy_sata_cfg_lanes()
1060 		val = RXTX_REG61_LOADFREQ_SHIFT_SET(val, 0x0);  in xgene_phy_sata_cfg_lanes()
1061 		val = RXTX_REG61_EYE_COUNT_WIDTH_SEL_SET(val, 0x0);  in xgene_phy_sata_cfg_lanes()
1062 		serdes_wr(ctx, lane, RXTX_REG61, val);  in xgene_phy_sata_cfg_lanes()
1064 		serdes_rd(ctx, lane, RXTX_REG62, &val);  in xgene_phy_sata_cfg_lanes()
1065 		val = RXTX_REG62_PERIOD_H1_QLATCH_SET(val, 0x0);  in xgene_phy_sata_cfg_lanes()
1066 		serdes_wr(ctx, lane, RXTX_REG62, val);  in xgene_phy_sata_cfg_lanes()
1071 			serdes_rd(ctx, lane, reg, &val);  in xgene_phy_sata_cfg_lanes()
1072 			val = RXTX_REG89_MU_TH7_SET(val, 0xe);  in xgene_phy_sata_cfg_lanes()
1073 			val = RXTX_REG89_MU_TH8_SET(val, 0xe);  in xgene_phy_sata_cfg_lanes()
1074 			val = RXTX_REG89_MU_TH9_SET(val, 0xe);  in xgene_phy_sata_cfg_lanes()
1075 			serdes_wr(ctx, lane, reg, val);  in xgene_phy_sata_cfg_lanes()
1081 			serdes_rd(ctx, lane, reg, &val);  in xgene_phy_sata_cfg_lanes()
1082 			val = RXTX_REG96_MU_FREQ1_SET(val, 0x10);  in xgene_phy_sata_cfg_lanes()
1083 			val = RXTX_REG96_MU_FREQ2_SET(val, 0x10);  in xgene_phy_sata_cfg_lanes()
1084 			val = RXTX_REG96_MU_FREQ3_SET(val, 0x10);  in xgene_phy_sata_cfg_lanes()
1085 			serdes_wr(ctx, lane, reg, val);  in xgene_phy_sata_cfg_lanes()
1091 			serdes_rd(ctx, lane, reg, &val);  in xgene_phy_sata_cfg_lanes()
1092 			val = RXTX_REG99_MU_PHASE1_SET(val, 0x7);  in xgene_phy_sata_cfg_lanes()
1093 			val = RXTX_REG99_MU_PHASE2_SET(val, 0x7);  in xgene_phy_sata_cfg_lanes()
1094 			val = RXTX_REG99_MU_PHASE3_SET(val, 0x7);  in xgene_phy_sata_cfg_lanes()
1095 			serdes_wr(ctx, lane, reg, val);  in xgene_phy_sata_cfg_lanes()
1098 		serdes_rd(ctx, lane, RXTX_REG102, &val);  in xgene_phy_sata_cfg_lanes()
1099 		val = RXTX_REG102_FREQLOOP_LIMIT_SET(val, 0x0);  in xgene_phy_sata_cfg_lanes()
1100 		serdes_wr(ctx, lane, RXTX_REG102, val);  in xgene_phy_sata_cfg_lanes()
1104 		serdes_rd(ctx, lane, RXTX_REG125, &val);  in xgene_phy_sata_cfg_lanes()
1105 		val = RXTX_REG125_SIGN_PQ_SET(val,  in xgene_phy_sata_cfg_lanes()
1108 		val = RXTX_REG125_PQ_REG_SET(val,  in xgene_phy_sata_cfg_lanes()
1111 		val = RXTX_REG125_PHZ_MANUAL_SET(val, 0x1);  in xgene_phy_sata_cfg_lanes()
1112 		serdes_wr(ctx, lane, RXTX_REG125, val);  in xgene_phy_sata_cfg_lanes()
1114 		serdes_rd(ctx, lane, RXTX_REG127, &val);  in xgene_phy_sata_cfg_lanes()
1115 		val = RXTX_REG127_LATCH_MAN_CAL_ENA_SET(val, 0x0);  in xgene_phy_sata_cfg_lanes()
1116 		serdes_wr(ctx, lane, RXTX_REG127, val);  in xgene_phy_sata_cfg_lanes()
1118 		serdes_rd(ctx, lane, RXTX_REG128, &val);  in xgene_phy_sata_cfg_lanes()
1119 		val = RXTX_REG128_LATCH_CAL_WAIT_SEL_SET(val, 0x3);  in xgene_phy_sata_cfg_lanes()
1120 		serdes_wr(ctx, lane, RXTX_REG128, val);  in xgene_phy_sata_cfg_lanes()
1122 		serdes_rd(ctx, lane, RXTX_REG145, &val);  in xgene_phy_sata_cfg_lanes()
1123 		val = RXTX_REG145_RXDFE_CONFIG_SET(val, 0x3);  in xgene_phy_sata_cfg_lanes()
1124 		val = RXTX_REG145_TX_IDLE_SATA_SET(val, 0x0);  in xgene_phy_sata_cfg_lanes()
1126 			val = RXTX_REG145_RXES_ENA_SET(val, 0x1);  in xgene_phy_sata_cfg_lanes()
1127 			val = RXTX_REG145_RXVWES_LATENA_SET(val, 0x1);  in xgene_phy_sata_cfg_lanes()
1129 			val = RXTX_REG145_RXES_ENA_SET(val, 0x0);  in xgene_phy_sata_cfg_lanes()
1130 			val = RXTX_REG145_RXVWES_LATENA_SET(val, 0x0);  in xgene_phy_sata_cfg_lanes()
1132 		serdes_wr(ctx, lane, RXTX_REG145, val);  in xgene_phy_sata_cfg_lanes()
1151 	u32 val;  in xgene_phy_cal_rdy_chk()  local
1165 		cmu_rd(ctx, cmu_type, CMU_REG1, &val);  in xgene_phy_cal_rdy_chk()
1166 		val = CMU_REG1_PLL_MANUALCAL_SET(val, 0x0);  in xgene_phy_cal_rdy_chk()
1167 		cmu_wr(ctx, cmu_type, CMU_REG1, val);  in xgene_phy_cal_rdy_chk()
1191 	cmu_rd(ctx, cmu_type, CMU_REG17, &val);  in xgene_phy_cal_rdy_chk()
1192 	val = CMU_REG17_PVT_CODE_R2A_SET(val, 0x12);  in xgene_phy_cal_rdy_chk()
1193 	val = CMU_REG17_RESERVED_7_SET(val, 0x0);  in xgene_phy_cal_rdy_chk()
1194 	cmu_wr(ctx, cmu_type, CMU_REG17, val);  in xgene_phy_cal_rdy_chk()
1202 	cmu_rd(ctx, cmu_type, CMU_REG17, &val);  in xgene_phy_cal_rdy_chk()
1203 	val = CMU_REG17_PVT_CODE_R2A_SET(val, 0x29);  in xgene_phy_cal_rdy_chk()
1204 	val = CMU_REG17_RESERVED_7_SET(val, 0x0);  in xgene_phy_cal_rdy_chk()
1205 	cmu_wr(ctx, cmu_type, CMU_REG17, val);  in xgene_phy_cal_rdy_chk()
1209 	cmu_rd(ctx, cmu_type, CMU_REG17, &val);  in xgene_phy_cal_rdy_chk()
1210 	val = CMU_REG17_PVT_CODE_R2A_SET(val, 0x28);  in xgene_phy_cal_rdy_chk()
1211 	val = CMU_REG17_RESERVED_7_SET(val, 0x0);  in xgene_phy_cal_rdy_chk()
1212 	cmu_wr(ctx, cmu_type, CMU_REG17, val);  in xgene_phy_cal_rdy_chk()
1220 		cmu_rd(ctx, cmu_type, CMU_REG7, &val);  in xgene_phy_cal_rdy_chk()
1221 		if (CMU_REG7_PLL_CALIB_DONE_RD(val))  in xgene_phy_cal_rdy_chk()
1230 	cmu_rd(ctx, cmu_type, CMU_REG7, &val);  in xgene_phy_cal_rdy_chk()
1232 		CMU_REG7_PLL_CALIB_DONE_RD(val) ? "done" : "failed");  in xgene_phy_cal_rdy_chk()
1233 	if (CMU_REG7_VCO_CAL_FAIL_RD(val)) {  in xgene_phy_cal_rdy_chk()
1240 	cmu_rd(ctx, cmu_type, CMU_REG15, &val);  in xgene_phy_cal_rdy_chk()
1241 	dev_dbg(ctx->dev, "PHY Tx is %sready\n", val & 0x300 ? "" : "not ");  in xgene_phy_cal_rdy_chk()
1249 	u32 val;  in xgene_phy_pdwn_force_vco()  local
1253 		cmu_rd(ctx, cmu_type, CMU_REG16, &val);  in xgene_phy_pdwn_force_vco()
1254 		val = CMU_REG16_VCOCAL_WAIT_BTW_CODE_SET(val, 0x7);  in xgene_phy_pdwn_force_vco()
1255 		cmu_wr(ctx, cmu_type, CMU_REG16, val);  in xgene_phy_pdwn_force_vco()
1267 	u32 val;  in xgene_phy_hw_init_sata()  local
1274 	val = readl(sds_base + SATA_ENET_SDS_RST_CTL);	/* Force a barrier */  in xgene_phy_hw_init_sata()
1283 	val = readl(sds_base + SATA_ENET_SDS_CTL1);  in xgene_phy_hw_init_sata()
1284 	val = CFG_I_SPD_SEL_CDR_OVR1_SET(val,  in xgene_phy_hw_init_sata()
1286 	writel(val, sds_base + SATA_ENET_SDS_CTL1);  in xgene_phy_hw_init_sata()
1289 	val = readl(sds_base + SATA_ENET_SDS_CTL0);  in xgene_phy_hw_init_sata()
1290 	val = REGSPEC_CFG_I_CUSTOMER_PIN_MODE0_SET(val, 0x4421);  in xgene_phy_hw_init_sata()
1291 	writel(val, sds_base + SATA_ENET_SDS_CTL0);  in xgene_phy_hw_init_sata()
1307 	val = readl(sds_base + SATA_ENET_SDS_PCS_CTL0);  in xgene_phy_hw_init_sata()
1308 	val = REGSPEC_CFG_I_RX_WORDMODE0_SET(val, 0x3);  in xgene_phy_hw_init_sata()
1309 	val = REGSPEC_CFG_I_TX_WORDMODE0_SET(val, 0x3);  in xgene_phy_hw_init_sata()
1310 	writel(val, sds_base + SATA_ENET_SDS_PCS_CTL0);  in xgene_phy_hw_init_sata()
1359 		u32 val;  in xgene_phy_force_lat_summer_cal()  member
1417 			  serdes_reg[i].val);  in xgene_phy_force_lat_summer_cal()
1446 	u32 val;  in xgene_phy_gen_avg_val()  local
1470 		serdes_rd(ctx, lane, RXTX_REG21, &val);  in xgene_phy_gen_avg_val()
1471 		lat_do_itr = RXTX_REG21_DO_LATCH_CALOUT_RD(val);  in xgene_phy_gen_avg_val()
1472 		lat_xo_itr = RXTX_REG21_XO_LATCH_CALOUT_RD(val);  in xgene_phy_gen_avg_val()
1473 		fail_odd = RXTX_REG21_LATCH_CAL_FAIL_ODD_RD(val);  in xgene_phy_gen_avg_val()
1475 		serdes_rd(ctx, lane, RXTX_REG22, &val);  in xgene_phy_gen_avg_val()
1476 		lat_eo_itr = RXTX_REG22_EO_LATCH_CALOUT_RD(val);  in xgene_phy_gen_avg_val()
1477 		lat_so_itr = RXTX_REG22_SO_LATCH_CALOUT_RD(val);  in xgene_phy_gen_avg_val()
1478 		fail_even = RXTX_REG22_LATCH_CAL_FAIL_EVEN_RD(val);  in xgene_phy_gen_avg_val()
1480 		serdes_rd(ctx, lane, RXTX_REG23, &val);  in xgene_phy_gen_avg_val()
1481 		lat_de_itr = RXTX_REG23_DE_LATCH_CALOUT_RD(val);  in xgene_phy_gen_avg_val()
1482 		lat_xe_itr = RXTX_REG23_XE_LATCH_CALOUT_RD(val);  in xgene_phy_gen_avg_val()
1484 		serdes_rd(ctx, lane, RXTX_REG24, &val);  in xgene_phy_gen_avg_val()
1485 		lat_ee_itr = RXTX_REG24_EE_LATCH_CALOUT_RD(val);  in xgene_phy_gen_avg_val()
1486 		lat_se_itr = RXTX_REG24_SE_LATCH_CALOUT_RD(val);  in xgene_phy_gen_avg_val()
1488 		serdes_rd(ctx, lane, RXTX_REG121, &val);  in xgene_phy_gen_avg_val()
1489 		sum_cal_itr = RXTX_REG121_SUMOS_CAL_CODE_RD(val);  in xgene_phy_gen_avg_val()
1522 	serdes_rd(ctx, lane, RXTX_REG127, &val);  in xgene_phy_gen_avg_val()
1523 	val = RXTX_REG127_DO_LATCH_MANCAL_SET(val,  in xgene_phy_gen_avg_val()
1525 	val = RXTX_REG127_XO_LATCH_MANCAL_SET(val,  in xgene_phy_gen_avg_val()
1527 	serdes_wr(ctx, lane, RXTX_REG127, val);  in xgene_phy_gen_avg_val()
1529 	serdes_rd(ctx, lane, RXTX_REG128, &val);  in xgene_phy_gen_avg_val()
1530 	val = RXTX_REG128_EO_LATCH_MANCAL_SET(val,  in xgene_phy_gen_avg_val()
1532 	val = RXTX_REG128_SO_LATCH_MANCAL_SET(val,  in xgene_phy_gen_avg_val()
1534 	serdes_wr(ctx, lane, RXTX_REG128, val);  in xgene_phy_gen_avg_val()
1536 	serdes_rd(ctx, lane, RXTX_REG129, &val);  in xgene_phy_gen_avg_val()
1537 	val = RXTX_REG129_DE_LATCH_MANCAL_SET(val,  in xgene_phy_gen_avg_val()
1539 	val = RXTX_REG129_XE_LATCH_MANCAL_SET(val,  in xgene_phy_gen_avg_val()
1541 	serdes_wr(ctx, lane, RXTX_REG129, val);  in xgene_phy_gen_avg_val()
1543 	serdes_rd(ctx, lane, RXTX_REG130, &val);  in xgene_phy_gen_avg_val()
1544 	val = RXTX_REG130_EE_LATCH_MANCAL_SET(val,  in xgene_phy_gen_avg_val()
1546 	val = RXTX_REG130_SE_LATCH_MANCAL_SET(val,  in xgene_phy_gen_avg_val()
1548 	serdes_wr(ctx, lane, RXTX_REG130, val);  in xgene_phy_gen_avg_val()
1551 	serdes_rd(ctx, lane, RXTX_REG14, &val);  in xgene_phy_gen_avg_val()
1552 	val = RXTX_REG14_CLTE_LATCAL_MAN_PROG_SET(val,  in xgene_phy_gen_avg_val()
1554 	serdes_wr(ctx, lane, RXTX_REG14, val);  in xgene_phy_gen_avg_val()
1570 	serdes_rd(ctx, lane, RXTX_REG14, &val);  in xgene_phy_gen_avg_val()
1571 	val = RXTX_REG14_CTLE_LATCAL_MAN_ENA_SET(val, 0x1);  in xgene_phy_gen_avg_val()
1572 	serdes_wr(ctx, lane, RXTX_REG14, val);  in xgene_phy_gen_avg_val()
1575 	serdes_rd(ctx, lane, RXTX_REG127, &val);  in xgene_phy_gen_avg_val()
1576 	val = RXTX_REG127_LATCH_MAN_CAL_ENA_SET(val, 0x1);  in xgene_phy_gen_avg_val()
1578 	serdes_wr(ctx, lane, RXTX_REG127, val);  in xgene_phy_gen_avg_val()
1581 	serdes_rd(ctx, lane, RXTX_REG12, &val);  in xgene_phy_gen_avg_val()
1582 	val = RXTX_REG12_RX_DET_TERM_ENABLE_SET(val, 0);  in xgene_phy_gen_avg_val()
1583 	serdes_wr(ctx, lane, RXTX_REG12, val);  in xgene_phy_gen_avg_val()