408 	struct st_gpio_bank *bank = gpio_range_to_bank(range);  in st_get_pio_control()  local
410 	return &bank->pc;  in st_get_pio_control()
706 static inline void __st_gpio_set(struct st_gpio_bank *bank,  in __st_gpio_set()  argument
710 		writel(BIT(offset), bank->base + REG_PIO_SET_POUT);  in __st_gpio_set()
712 		writel(BIT(offset), bank->base + REG_PIO_CLR_POUT);  in __st_gpio_set()
715 static void st_gpio_direction(struct st_gpio_bank *bank,  in st_gpio_direction()  argument
739 			writel(BIT(offset), bank->base + REG_PIO_SET_PC(i));  in st_gpio_direction()
741 			writel(BIT(offset), bank->base + REG_PIO_CLR_PC(i));  in st_gpio_direction()
757 	struct st_gpio_bank *bank = gpio_chip_to_bank(chip);  in st_gpio_get()  local
759 	return !!(readl(bank->base + REG_PIO_PIN) & BIT(offset));  in st_gpio_get()
764 	struct st_gpio_bank *bank = gpio_chip_to_bank(chip);  in st_gpio_set()  local
765 	__st_gpio_set(bank, offset, value);  in st_gpio_set()
778 	struct st_gpio_bank *bank = gpio_chip_to_bank(chip);  in st_gpio_direction_output()  local
780 	__st_gpio_set(bank, offset, value);  in st_gpio_direction_output()
788 	struct st_gpio_bank *bank = gpio_chip_to_bank(chip);  in st_gpio_get_direction()  local
789 	struct st_pio_control pc = bank->pc;  in st_gpio_get_direction()
808 		value = readl(bank->base + REG_PIO_PC(i));  in st_gpio_get_direction()
982 	struct st_gpio_bank *bank = gpio_range_to_bank(range);  in st_pmx_set_gpio_direction()  local
988 	st_pctl_set_function(&bank->pc, gpio, 0);  in st_pmx_set_gpio_direction()
989 	st_gpio_direction(bank, gpio, input ?  in st_pmx_set_gpio_direction()
1112 	int bank, struct st_pio_control *pc)  in st_pctl_dt_setup_retime_packed()  argument
1118 	int reg = (data->rt + bank * RT_P_CFGS_PER_BANK) * 4;  in st_pctl_dt_setup_retime_packed()
1148 	int bank, struct st_pio_control *pc)  in st_pctl_dt_setup_retime_dedicated()  argument
1154 	int reg_offset = (data->rt + bank * RT_D_CFGS_PER_BANK) * 4;  in st_pctl_dt_setup_retime_dedicated()
1172 	int bank, struct st_pio_control *pc)  in st_pctl_dt_setup_retime()  argument
1176 		return st_pctl_dt_setup_retime_packed(info, bank, pc);  in st_pctl_dt_setup_retime()
1178 		return st_pctl_dt_setup_retime_dedicated(info, bank, pc);  in st_pctl_dt_setup_retime()
1185 					    struct regmap *regmap, int bank,  in st_pc_get_value()  argument
1188 	struct reg_field reg = REG_FIELD((data + bank) * 4, lsb, msb);  in st_pc_get_value()
1196 static void st_parse_syscfgs(struct st_pinctrl *info, int bank,  in st_parse_syscfgs()  argument
1205 	int lsb = (bank%4) * ST_GPIO_PINS_PER_BANK;  in st_parse_syscfgs()
1207 	struct st_pio_control *pc = &info->banks[bank].pc;  in st_parse_syscfgs()
1211 	pc->alt = st_pc_get_value(dev, regmap, bank, data->alt, 0, 31);  in st_parse_syscfgs()
1212 	pc->oe = st_pc_get_value(dev, regmap, bank/4, data->oe, lsb, msb);  in st_parse_syscfgs()
1213 	pc->pu = st_pc_get_value(dev, regmap, bank/4, data->pu, lsb, msb);  in st_parse_syscfgs()
1214 	pc->od = st_pc_get_value(dev, regmap, bank/4, data->od, lsb, msb);  in st_parse_syscfgs()
1219 	st_pctl_dt_setup_retime(info, bank, pc);  in st_parse_syscfgs()
1338 	struct st_gpio_bank *bank = gpio_chip_to_bank(gc);  in st_gpio_irq_mask()  local
1340 	writel(BIT(d->hwirq), bank->base + REG_PIO_CLR_PMASK);  in st_gpio_irq_mask()
1346 	struct st_gpio_bank *bank = gpio_chip_to_bank(gc);  in st_gpio_irq_unmask()  local
1348 	writel(BIT(d->hwirq), bank->base + REG_PIO_SET_PMASK);  in st_gpio_irq_unmask()
1354 	struct st_gpio_bank *bank = gpio_chip_to_bank(gc);  in st_gpio_irq_set_type()  local
1376 		comp = st_gpio_get(&bank->gpio_chip, pin);  in st_gpio_irq_set_type()
1383 	spin_lock_irqsave(&bank->lock, flags);  in st_gpio_irq_set_type()
1384 	bank->irq_edge_conf &=  ~(ST_IRQ_EDGE_MASK << (  in st_gpio_irq_set_type()
1386 	bank->irq_edge_conf |= pin_edge_conf;  in st_gpio_irq_set_type()
1387 	spin_unlock_irqrestore(&bank->lock, flags);  in st_gpio_irq_set_type()
1389 	val = readl(bank->base + REG_PIO_PCOMP);  in st_gpio_irq_set_type()
1392 	writel(val, bank->base + REG_PIO_PCOMP);  in st_gpio_irq_set_type()
1421 static void __gpio_irq_handler(struct st_gpio_bank *bank)  in __gpio_irq_handler()  argument
1427 	spin_lock_irqsave(&bank->lock, flags);  in __gpio_irq_handler()
1428 	bank_edge_mask = bank->irq_edge_conf;  in __gpio_irq_handler()
1429 	spin_unlock_irqrestore(&bank->lock, flags);  in __gpio_irq_handler()
1432 		port_in = readl(bank->base + REG_PIO_PIN);  in __gpio_irq_handler()
1433 		port_comp = readl(bank->base + REG_PIO_PCOMP);  in __gpio_irq_handler()
1434 		port_mask = readl(bank->base + REG_PIO_PMASK);  in __gpio_irq_handler()
1447 				val = st_gpio_get(&bank->gpio_chip, n);  in __gpio_irq_handler()
1450 					val ? bank->base + REG_PIO_SET_PCOMP :  in __gpio_irq_handler()
1451 					bank->base + REG_PIO_CLR_PCOMP);  in __gpio_irq_handler()
1458 			generic_handle_irq(irq_find_mapping(bank->gpio_chip.irqdomain, n));  in __gpio_irq_handler()
1468 	struct st_gpio_bank *bank = gpio_chip_to_bank(gc);  in st_gpio_irq_handler()  local
1471 	__gpio_irq_handler(bank);  in st_gpio_irq_handler()
1517 	struct st_gpio_bank *bank = &info->banks[bank_nr];  in st_gpiolib_register_bank()  local
1518 	struct pinctrl_gpio_range *range = &bank->range;  in st_gpiolib_register_bank()
1527 	bank->base = devm_ioremap_resource(dev, &res);  in st_gpiolib_register_bank()
1528 	if (IS_ERR(bank->base))  in st_gpiolib_register_bank()
1529 		return PTR_ERR(bank->base);  in st_gpiolib_register_bank()
1531 	bank->gpio_chip = st_gpio_template;  in st_gpiolib_register_bank()
1532 	bank->gpio_chip.base = bank_num * ST_GPIO_PINS_PER_BANK;  in st_gpiolib_register_bank()
1533 	bank->gpio_chip.ngpio = ST_GPIO_PINS_PER_BANK;  in st_gpiolib_register_bank()
1534 	bank->gpio_chip.of_node = np;  in st_gpiolib_register_bank()
1535 	bank->gpio_chip.dev = dev;  in st_gpiolib_register_bank()
1536 	spin_lock_init(&bank->lock);  in st_gpiolib_register_bank()
1539 	bank->gpio_chip.label = range->name;  in st_gpiolib_register_bank()
1543 	range->npins = bank->gpio_chip.ngpio;  in st_gpiolib_register_bank()
1544 	range->gc = &bank->gpio_chip;  in st_gpiolib_register_bank()
1545 	err  = gpiochip_add(&bank->gpio_chip);  in st_gpiolib_register_bank()
1573 		gpiochip_set_chained_irqchip(&bank->gpio_chip, &st_gpio_irqchip,  in st_gpiolib_register_bank()
1578 		err = gpiochip_irqchip_add(&bank->gpio_chip, &st_gpio_irqchip,  in st_gpiolib_register_bank()
1582 			gpiochip_remove(&bank->gpio_chip);  in st_gpiolib_register_bank()
1617 	int i = 0, j = 0, k = 0, bank;  in st_pctl_probe_dt()  local
1677 	bank = 0;  in st_pctl_probe_dt()
1681 			ret = st_gpiolib_register_bank(info, bank, child);  in st_pctl_probe_dt()
1685 			k = info->banks[bank].range.pin_base;  in st_pctl_probe_dt()
1686 			bank_name = info->banks[bank].range.name;  in st_pctl_probe_dt()
1693 			st_parse_syscfgs(info, bank, child);  in st_pctl_probe_dt()
1694 			bank++;  in st_pctl_probe_dt()