Lines Matching refs:TB10X_PORT5
40 #define TB10X_PORT5 (128) macro
101 PINCTRL_PIN(TB10X_PORT5 + 0, "PC_CE1N"),
102 PINCTRL_PIN(TB10X_PORT5 + 1, "PC_CE2N"),
103 PINCTRL_PIN(TB10X_PORT5 + 2, "PC_REGN"),
104 PINCTRL_PIN(TB10X_PORT5 + 3, "PC_INPACKN"),
105 PINCTRL_PIN(TB10X_PORT5 + 4, "PC_OEN"),
106 PINCTRL_PIN(TB10X_PORT5 + 5, "PC_WEN"),
107 PINCTRL_PIN(TB10X_PORT5 + 6, "PC_IORDN"),
108 PINCTRL_PIN(TB10X_PORT5 + 7, "PC_IOWRN"),
109 PINCTRL_PIN(TB10X_PORT5 + 8, "PC_RDYIRQN"),
110 PINCTRL_PIN(TB10X_PORT5 + 9, "PC_WAITN"),
111 PINCTRL_PIN(TB10X_PORT5 + 10, "PC_A0"),
112 PINCTRL_PIN(TB10X_PORT5 + 11, "PC_A1"),
113 PINCTRL_PIN(TB10X_PORT5 + 12, "PC_A2"),
114 PINCTRL_PIN(TB10X_PORT5 + 13, "PC_A3"),
115 PINCTRL_PIN(TB10X_PORT5 + 14, "PC_A4"),
116 PINCTRL_PIN(TB10X_PORT5 + 15, "PC_A5"),
117 PINCTRL_PIN(TB10X_PORT5 + 16, "PC_A6"),
118 PINCTRL_PIN(TB10X_PORT5 + 17, "PC_A7"),
119 PINCTRL_PIN(TB10X_PORT5 + 18, "PC_A8"),
120 PINCTRL_PIN(TB10X_PORT5 + 19, "PC_A9"),
121 PINCTRL_PIN(TB10X_PORT5 + 20, "PC_A10"),
122 PINCTRL_PIN(TB10X_PORT5 + 21, "PC_A11"),
123 PINCTRL_PIN(TB10X_PORT5 + 22, "PC_A12"),
124 PINCTRL_PIN(TB10X_PORT5 + 23, "PC_A13"),
125 PINCTRL_PIN(TB10X_PORT5 + 24, "PC_A14"),
126 PINCTRL_PIN(TB10X_PORT5 + 25, "PC_D0"),
127 PINCTRL_PIN(TB10X_PORT5 + 26, "PC_D1"),
128 PINCTRL_PIN(TB10X_PORT5 + 27, "PC_D2"),
129 PINCTRL_PIN(TB10X_PORT5 + 28, "PC_D3"),
130 PINCTRL_PIN(TB10X_PORT5 + 29, "PC_D4"),
131 PINCTRL_PIN(TB10X_PORT5 + 30, "PC_D5"),
132 PINCTRL_PIN(TB10X_PORT5 + 31, "PC_D6"),
133 PINCTRL_PIN(TB10X_PORT5 + 32, "PC_D7"),
134 PINCTRL_PIN(TB10X_PORT5 + 33, "PC_MOSTRT"),
135 PINCTRL_PIN(TB10X_PORT5 + 34, "PC_MOVAL"),
136 PINCTRL_PIN(TB10X_PORT5 + 35, "PC_MDO0"),
137 PINCTRL_PIN(TB10X_PORT5 + 36, "PC_MDO1"),
138 PINCTRL_PIN(TB10X_PORT5 + 37, "PC_MDO2"),
139 PINCTRL_PIN(TB10X_PORT5 + 38, "PC_MDO3"),
140 PINCTRL_PIN(TB10X_PORT5 + 39, "PC_MDO4"),
141 PINCTRL_PIN(TB10X_PORT5 + 40, "PC_MDO5"),
142 PINCTRL_PIN(TB10X_PORT5 + 41, "PC_MDO6"),
143 PINCTRL_PIN(TB10X_PORT5 + 42, "PC_MDO7"),
144 PINCTRL_PIN(TB10X_PORT5 + 43, "PC_MISTRT"),
145 PINCTRL_PIN(TB10X_PORT5 + 44, "PC_MIVAL"),
146 PINCTRL_PIN(TB10X_PORT5 + 45, "PC_MDI0"),
147 PINCTRL_PIN(TB10X_PORT5 + 46, "PC_MDI1"),
148 PINCTRL_PIN(TB10X_PORT5 + 47, "PC_MDI2"),
149 PINCTRL_PIN(TB10X_PORT5 + 48, "PC_MDI3"),
150 PINCTRL_PIN(TB10X_PORT5 + 49, "PC_MDI4"),
151 PINCTRL_PIN(TB10X_PORT5 + 50, "PC_MDI5"),
152 PINCTRL_PIN(TB10X_PORT5 + 51, "PC_MDI6"),
153 PINCTRL_PIN(TB10X_PORT5 + 52, "PC_MDI7"),
154 PINCTRL_PIN(TB10X_PORT5 + 53, "PC_MICLK"),
316 static const unsigned gpioj_pins[] = { TB10X_PORT5 + 0, TB10X_PORT5 + 1,
317 TB10X_PORT5 + 2, TB10X_PORT5 + 3,
318 TB10X_PORT5 + 4, TB10X_PORT5 + 5,
319 TB10X_PORT5 + 6, TB10X_PORT5 + 7,
320 TB10X_PORT5 + 8, TB10X_PORT5 + 9,
321 TB10X_PORT5 + 10, TB10X_PORT5 + 11,
322 TB10X_PORT5 + 12, TB10X_PORT5 + 13,
323 TB10X_PORT5 + 14, TB10X_PORT5 + 15,
324 TB10X_PORT5 + 16, TB10X_PORT5 + 17,
325 TB10X_PORT5 + 18, TB10X_PORT5 + 19,
326 TB10X_PORT5 + 20, TB10X_PORT5 + 21,
327 TB10X_PORT5 + 22, TB10X_PORT5 + 23,
328 TB10X_PORT5 + 24, TB10X_PORT5 + 25,
329 TB10X_PORT5 + 26, TB10X_PORT5 + 27,
330 TB10X_PORT5 + 28, TB10X_PORT5 + 29,
331 TB10X_PORT5 + 30, TB10X_PORT5 + 31};
332 static const unsigned gpiok_pins[] = { TB10X_PORT5 + 32, TB10X_PORT5 + 33,
333 TB10X_PORT5 + 34, TB10X_PORT5 + 35,
334 TB10X_PORT5 + 36, TB10X_PORT5 + 37,
335 TB10X_PORT5 + 38, TB10X_PORT5 + 39,
336 TB10X_PORT5 + 40, TB10X_PORT5 + 41,
337 TB10X_PORT5 + 42, TB10X_PORT5 + 43,
338 TB10X_PORT5 + 44, TB10X_PORT5 + 45,
339 TB10X_PORT5 + 46, TB10X_PORT5 + 47,
340 TB10X_PORT5 + 48, TB10X_PORT5 + 49,
341 TB10X_PORT5 + 50, TB10X_PORT5 + 51,
342 TB10X_PORT5 + 52, TB10X_PORT5 + 53};
343 static const unsigned ciplus_pins[] = { TB10X_PORT5 + 0, TB10X_PORT5 + 1,
344 TB10X_PORT5 + 2, TB10X_PORT5 + 3,
345 TB10X_PORT5 + 4, TB10X_PORT5 + 5,
346 TB10X_PORT5 + 6, TB10X_PORT5 + 7,
347 TB10X_PORT5 + 8, TB10X_PORT5 + 9,
348 TB10X_PORT5 + 10, TB10X_PORT5 + 11,
349 TB10X_PORT5 + 12, TB10X_PORT5 + 13,
350 TB10X_PORT5 + 14, TB10X_PORT5 + 15,
351 TB10X_PORT5 + 16, TB10X_PORT5 + 17,
352 TB10X_PORT5 + 18, TB10X_PORT5 + 19,
353 TB10X_PORT5 + 20, TB10X_PORT5 + 21,
354 TB10X_PORT5 + 22, TB10X_PORT5 + 23,
355 TB10X_PORT5 + 24, TB10X_PORT5 + 25,
356 TB10X_PORT5 + 26, TB10X_PORT5 + 27,
357 TB10X_PORT5 + 28, TB10X_PORT5 + 29,
358 TB10X_PORT5 + 30, TB10X_PORT5 + 31,
359 TB10X_PORT5 + 32, TB10X_PORT5 + 33,
360 TB10X_PORT5 + 34, TB10X_PORT5 + 35,
361 TB10X_PORT5 + 36, TB10X_PORT5 + 37,
362 TB10X_PORT5 + 38, TB10X_PORT5 + 39,
363 TB10X_PORT5 + 40, TB10X_PORT5 + 41,
364 TB10X_PORT5 + 42, TB10X_PORT5 + 43,
365 TB10X_PORT5 + 44, TB10X_PORT5 + 45,
366 TB10X_PORT5 + 46, TB10X_PORT5 + 47,
367 TB10X_PORT5 + 48, TB10X_PORT5 + 49,
368 TB10X_PORT5 + 50, TB10X_PORT5 + 51,
369 TB10X_PORT5 + 52, TB10X_PORT5 + 53};
370 static const unsigned mcard_pins[] = { TB10X_PORT5 + 3, TB10X_PORT5 + 10,
371 TB10X_PORT5 + 11, TB10X_PORT5 + 12,
372 TB10X_PORT5 + 22, TB10X_PORT5 + 23,
373 TB10X_PORT5 + 33, TB10X_PORT5 + 35,
374 TB10X_PORT5 + 36, TB10X_PORT5 + 37,
375 TB10X_PORT5 + 38, TB10X_PORT5 + 39,
376 TB10X_PORT5 + 40, TB10X_PORT5 + 41,
377 TB10X_PORT5 + 42, TB10X_PORT5 + 43,
378 TB10X_PORT5 + 45, TB10X_PORT5 + 46,
379 TB10X_PORT5 + 47, TB10X_PORT5 + 48,
380 TB10X_PORT5 + 49, TB10X_PORT5 + 50,
381 TB10X_PORT5 + 51, TB10X_PORT5 + 52,
382 TB10X_PORT5 + 53};
383 static const unsigned stc0_pins[] = { TB10X_PORT5 + 34, TB10X_PORT5 + 35,
384 TB10X_PORT5 + 36, TB10X_PORT5 + 37,
385 TB10X_PORT5 + 38, TB10X_PORT5 + 39,
386 TB10X_PORT5 + 40};
387 static const unsigned stc1_pins[] = { TB10X_PORT5 + 25, TB10X_PORT5 + 26,
388 TB10X_PORT5 + 27, TB10X_PORT5 + 28,
389 TB10X_PORT5 + 29, TB10X_PORT5 + 30,
390 TB10X_PORT5 + 44};