145 	u32 val;  in msm_pinmux_set_mux()  local
160 	val = readl(pctrl->regs + g->ctl_reg);  in msm_pinmux_set_mux()
161 	val &= ~(0x7 << g->mux_bit);  in msm_pinmux_set_mux()
162 	val |= i << g->mux_bit;  in msm_pinmux_set_mux()
163 	writel(val, pctrl->regs + g->ctl_reg);  in msm_pinmux_set_mux()
212 static unsigned msm_regval_to_drive(u32 val)  in msm_regval_to_drive()  argument
214 	return (val + 1) * 2;  in msm_regval_to_drive()
228 	u32 val;  in msm_config_group_get()  local
236 	val = readl(pctrl->regs + g->ctl_reg);  in msm_config_group_get()
237 	arg = (val >> bit) & mask;  in msm_config_group_get()
261 		val = readl(pctrl->regs + g->io_reg);  in msm_config_group_get()
262 		arg = !!(val & BIT(g->in_bit));  in msm_config_group_get()
292 	u32 val;  in msm_config_group_set()  local
329 			val = readl(pctrl->regs + g->io_reg);  in msm_config_group_set()
331 				val |= BIT(g->out_bit);  in msm_config_group_set()
333 				val &= ~BIT(g->out_bit);  in msm_config_group_set()
334 			writel(val, pctrl->regs + g->io_reg);  in msm_config_group_set()
357 		val = readl(pctrl->regs + g->ctl_reg);  in msm_config_group_set()
358 		val &= ~(mask << bit);  in msm_config_group_set()
359 		val |= arg << bit;  in msm_config_group_set()
360 		writel(val, pctrl->regs + g->ctl_reg);  in msm_config_group_set()
385 	u32 val;  in msm_gpio_direction_input()  local
391 	val = readl(pctrl->regs + g->ctl_reg);  in msm_gpio_direction_input()
392 	val &= ~BIT(g->oe_bit);  in msm_gpio_direction_input()
393 	writel(val, pctrl->regs + g->ctl_reg);  in msm_gpio_direction_input()
405 	u32 val;  in msm_gpio_direction_output()  local
411 	val = readl(pctrl->regs + g->io_reg);  in msm_gpio_direction_output()
413 		val |= BIT(g->out_bit);  in msm_gpio_direction_output()
415 		val &= ~BIT(g->out_bit);  in msm_gpio_direction_output()
416 	writel(val, pctrl->regs + g->io_reg);  in msm_gpio_direction_output()
418 	val = readl(pctrl->regs + g->ctl_reg);  in msm_gpio_direction_output()
419 	val |= BIT(g->oe_bit);  in msm_gpio_direction_output()
420 	writel(val, pctrl->regs + g->ctl_reg);  in msm_gpio_direction_output()
431 	u32 val;  in msm_gpio_get()  local
435 	val = readl(pctrl->regs + g->io_reg);  in msm_gpio_get()
436 	return !!(val & BIT(g->in_bit));  in msm_gpio_get()
444 	u32 val;  in msm_gpio_set()  local
450 	val = readl(pctrl->regs + g->io_reg);  in msm_gpio_set()
452 		val |= BIT(g->out_bit);  in msm_gpio_set()
454 		val &= ~BIT(g->out_bit);  in msm_gpio_set()
455 	writel(val, pctrl->regs + g->io_reg);  in msm_gpio_set()
559 	unsigned val, val2, intstat;  in msm_gpio_update_dual_edge_pos()  local
563 		val = readl(pctrl->regs + g->io_reg) & BIT(g->in_bit);  in msm_gpio_update_dual_edge_pos()
571 		if (intstat || (val == val2))  in msm_gpio_update_dual_edge_pos()
575 		val, val2);  in msm_gpio_update_dual_edge_pos()
584 	u32 val;  in msm_gpio_irq_mask()  local
590 	val = readl(pctrl->regs + g->intr_cfg_reg);  in msm_gpio_irq_mask()
591 	val &= ~BIT(g->intr_enable_bit);  in msm_gpio_irq_mask()
592 	writel(val, pctrl->regs + g->intr_cfg_reg);  in msm_gpio_irq_mask()
605 	u32 val;  in msm_gpio_irq_unmask()  local
611 	val = readl(pctrl->regs + g->intr_status_reg);  in msm_gpio_irq_unmask()
612 	val &= ~BIT(g->intr_status_bit);  in msm_gpio_irq_unmask()
613 	writel(val, pctrl->regs + g->intr_status_reg);  in msm_gpio_irq_unmask()
615 	val = readl(pctrl->regs + g->intr_cfg_reg);  in msm_gpio_irq_unmask()
616 	val |= BIT(g->intr_enable_bit);  in msm_gpio_irq_unmask()
617 	writel(val, pctrl->regs + g->intr_cfg_reg);  in msm_gpio_irq_unmask()
630 	u32 val;  in msm_gpio_irq_ack()  local
636 	val = readl(pctrl->regs + g->intr_status_reg);  in msm_gpio_irq_ack()
638 		val |= BIT(g->intr_status_bit);  in msm_gpio_irq_ack()
640 		val &= ~BIT(g->intr_status_bit);  in msm_gpio_irq_ack()
641 	writel(val, pctrl->regs + g->intr_status_reg);  in msm_gpio_irq_ack()
655 	u32 val;  in msm_gpio_irq_set_type()  local
670 	val = readl(pctrl->regs + g->intr_target_reg);  in msm_gpio_irq_set_type()
671 	val &= ~(7 << g->intr_target_bit);  in msm_gpio_irq_set_type()
672 	val |= g->intr_target_kpss_val << g->intr_target_bit;  in msm_gpio_irq_set_type()
673 	writel(val, pctrl->regs + g->intr_target_reg);  in msm_gpio_irq_set_type()
680 	val = readl(pctrl->regs + g->intr_cfg_reg);  in msm_gpio_irq_set_type()
681 	val |= BIT(g->intr_raw_status_bit);  in msm_gpio_irq_set_type()
683 		val &= ~(3 << g->intr_detection_bit);  in msm_gpio_irq_set_type()
684 		val &= ~(1 << g->intr_polarity_bit);  in msm_gpio_irq_set_type()
687 			val |= 1 << g->intr_detection_bit;  in msm_gpio_irq_set_type()
688 			val |= BIT(g->intr_polarity_bit);  in msm_gpio_irq_set_type()
691 			val |= 2 << g->intr_detection_bit;  in msm_gpio_irq_set_type()
692 			val |= BIT(g->intr_polarity_bit);  in msm_gpio_irq_set_type()
695 			val |= 3 << g->intr_detection_bit;  in msm_gpio_irq_set_type()
696 			val |= BIT(g->intr_polarity_bit);  in msm_gpio_irq_set_type()
701 			val |= BIT(g->intr_polarity_bit);  in msm_gpio_irq_set_type()
705 		val &= ~(1 << g->intr_detection_bit);  in msm_gpio_irq_set_type()
706 		val &= ~(1 << g->intr_polarity_bit);  in msm_gpio_irq_set_type()
709 			val |= BIT(g->intr_detection_bit);  in msm_gpio_irq_set_type()
710 			val |= BIT(g->intr_polarity_bit);  in msm_gpio_irq_set_type()
713 			val |= BIT(g->intr_detection_bit);  in msm_gpio_irq_set_type()
716 			val |= BIT(g->intr_detection_bit);  in msm_gpio_irq_set_type()
717 			val |= BIT(g->intr_polarity_bit);  in msm_gpio_irq_set_type()
722 			val |= BIT(g->intr_polarity_bit);  in msm_gpio_irq_set_type()
728 	writel(val, pctrl->regs + g->intr_cfg_reg);  in msm_gpio_irq_set_type()
775 	u32 val;  in msm_gpio_irq_handler()  local
786 		val = readl(pctrl->regs + g->intr_status_reg);  in msm_gpio_irq_handler()
787 		if (val & BIT(g->intr_status_bit)) {  in msm_gpio_irq_handler()