Lines Matching refs:BIT
27 #define BQ24190_REG_ISC_EN_HIZ_MASK BIT(7)
29 #define BQ24190_REG_ISC_VINDPM_MASK (BIT(6) | BIT(5) | BIT(4) | \
30 BIT(3))
32 #define BQ24190_REG_ISC_IINLIM_MASK (BIT(2) | BIT(1) | BIT(0))
36 #define BQ24190_REG_POC_RESET_MASK BIT(7)
38 #define BQ24190_REG_POC_WDT_RESET_MASK BIT(6)
40 #define BQ24190_REG_POC_CHG_CONFIG_MASK (BIT(5) | BIT(4))
42 #define BQ24190_REG_POC_SYS_MIN_MASK (BIT(3) | BIT(2) | BIT(1))
44 #define BQ24190_REG_POC_BOOST_LIM_MASK BIT(0)
48 #define BQ24190_REG_CCC_ICHG_MASK (BIT(7) | BIT(6) | BIT(5) | \
49 BIT(4) | BIT(3) | BIT(2))
51 #define BQ24190_REG_CCC_FORCE_20PCT_MASK BIT(0)
55 #define BQ24190_REG_PCTCC_IPRECHG_MASK (BIT(7) | BIT(6) | BIT(5) | \
56 BIT(4))
58 #define BQ24190_REG_PCTCC_ITERM_MASK (BIT(3) | BIT(2) | BIT(1) | \
59 BIT(0))
63 #define BQ24190_REG_CVC_VREG_MASK (BIT(7) | BIT(6) | BIT(5) | \
64 BIT(4) | BIT(3) | BIT(2))
66 #define BQ24190_REG_CVC_BATLOWV_MASK BIT(1)
68 #define BQ24190_REG_CVC_VRECHG_MASK BIT(0)
72 #define BQ24190_REG_CTTC_EN_TERM_MASK BIT(7)
74 #define BQ24190_REG_CTTC_TERM_STAT_MASK BIT(6)
76 #define BQ24190_REG_CTTC_WATCHDOG_MASK (BIT(5) | BIT(4))
78 #define BQ24190_REG_CTTC_EN_TIMER_MASK BIT(3)
80 #define BQ24190_REG_CTTC_CHG_TIMER_MASK (BIT(2) | BIT(1))
82 #define BQ24190_REG_CTTC_JEITA_ISET_MASK BIT(0)
86 #define BQ24190_REG_ICTRC_BAT_COMP_MASK (BIT(7) | BIT(6) | BIT(5))
88 #define BQ24190_REG_ICTRC_VCLAMP_MASK (BIT(4) | BIT(3) | BIT(2))
90 #define BQ24190_REG_ICTRC_TREG_MASK (BIT(1) | BIT(0))
94 #define BQ24190_REG_MOC_DPDM_EN_MASK BIT(7)
96 #define BQ24190_REG_MOC_TMR2X_EN_MASK BIT(6)
98 #define BQ24190_REG_MOC_BATFET_DISABLE_MASK BIT(5)
100 #define BQ24190_REG_MOC_JEITA_VSET_MASK BIT(4)
102 #define BQ24190_REG_MOC_INT_MASK_MASK (BIT(1) | BIT(0))
106 #define BQ24190_REG_SS_VBUS_STAT_MASK (BIT(7) | BIT(6))
108 #define BQ24190_REG_SS_CHRG_STAT_MASK (BIT(5) | BIT(4))
110 #define BQ24190_REG_SS_DPM_STAT_MASK BIT(3)
112 #define BQ24190_REG_SS_PG_STAT_MASK BIT(2)
114 #define BQ24190_REG_SS_THERM_STAT_MASK BIT(1)
116 #define BQ24190_REG_SS_VSYS_STAT_MASK BIT(0)
120 #define BQ24190_REG_F_WATCHDOG_FAULT_MASK BIT(7)
122 #define BQ24190_REG_F_BOOST_FAULT_MASK BIT(6)
124 #define BQ24190_REG_F_CHRG_FAULT_MASK (BIT(5) | BIT(4))
126 #define BQ24190_REG_F_BAT_FAULT_MASK BIT(3)
128 #define BQ24190_REG_F_NTC_FAULT_MASK (BIT(2) | BIT(1) | BIT(0))
132 #define BQ24190_REG_VPRS_PN_MASK (BIT(5) | BIT(4) | BIT(3))
137 #define BQ24190_REG_VPRS_TS_PROFILE_MASK BIT(2)
139 #define BQ24190_REG_VPRS_DEV_REG_MASK (BIT(1) | BIT(0))