Lines Matching refs:TWL4030_ADJUSTABLE_LDO

843 #define TWL4030_ADJUSTABLE_LDO(label, offset, num, turnon_delay, remap_conf) \  macro
955 TWL4030_ADJUSTABLE_LDO(VAUX1, 0x17, 1, 100, 0x08);
956 TWL4030_ADJUSTABLE_LDO(VAUX2_4030, 0x1b, 2, 100, 0x08);
957 TWL4030_ADJUSTABLE_LDO(VAUX2, 0x1b, 2, 100, 0x08);
958 TWL4030_ADJUSTABLE_LDO(VAUX3, 0x1f, 3, 100, 0x08);
959 TWL4030_ADJUSTABLE_LDO(VAUX4, 0x23, 4, 100, 0x08);
960 TWL4030_ADJUSTABLE_LDO(VMMC1, 0x27, 5, 100, 0x08);
961 TWL4030_ADJUSTABLE_LDO(VMMC2, 0x2b, 6, 100, 0x08);
962 TWL4030_ADJUSTABLE_LDO(VPLL1, 0x2f, 7, 100, 0x00);
963 TWL4030_ADJUSTABLE_LDO(VPLL2, 0x33, 8, 100, 0x08);
964 TWL4030_ADJUSTABLE_LDO(VSIM, 0x37, 9, 100, 0x00);
965 TWL4030_ADJUSTABLE_LDO(VDAC, 0x3b, 10, 100, 0x08);
966 TWL4030_ADJUSTABLE_LDO(VINTANA2, 0x43, 12, 100, 0x08);
967 TWL4030_ADJUSTABLE_LDO(VIO, 0x4b, 14, 1000, 0x08);