238 #define TW_OPSGL_IN(x,y) ((x << 5) | (y & 0x1f))  argument
239 #define TW_SGL_OUT(x) ((x >> 5) & 0x7)  argument
242 #define TW_RESID_OUT(x) ((x >> 4) & 0xff)  argument
245 #define TW_UNITHOST_IN(x,y) ((x << 4) | ( y & 0xf))  argument
246 #define TW_UNIT_OUT(x) (x & 0xf)  argument
249 #define TW_CONTROL_REG_ADDR(x) (x->base_addr)  argument
250 #define TW_STATUS_REG_ADDR(x) (x->base_addr + 0x4)  argument
251 #define TW_COMMAND_QUEUE_REG_ADDR(x) (x->base_addr + 0x8)  argument
252 #define TW_RESPONSE_QUEUE_REG_ADDR(x) (x->base_addr + 0xC)  argument
253 #define TW_CLEAR_ALL_INTERRUPTS(x) (outl(TW_STATUS_VALID_INTERRUPT, TW_CONTROL_REG_ADDR(x)))  argument
254 #define TW_CLEAR_ATTENTION_INTERRUPT(x) (outl(TW_CONTROL_CLEAR_ATTENTION_INTERRUPT, TW_CONTROL_REG_…  argument
255 #define TW_CLEAR_HOST_INTERRUPT(x) (outl(TW_CONTROL_CLEAR_HOST_INTERRUPT, TW_CONTROL_REG_ADDR(x)))  argument
256 #define TW_DISABLE_INTERRUPTS(x) (outl(TW_CONTROL_DISABLE_INTERRUPTS, TW_CONTROL_REG_ADDR(x)))  argument
257 …RRUPTS(x) (outl(TW_CONTROL_CLEAR_ATTENTION_INTERRUPT | TW_CONTROL_UNMASK_RESPONSE_INTERRUPT | TW_C…  argument
258 #define TW_MASK_COMMAND_INTERRUPT(x) (outl(TW_CONTROL_MASK_COMMAND_INTERRUPT, TW_CONTROL_REG_ADDR(x…  argument
259 #define TW_UNMASK_COMMAND_INTERRUPT(x) (outl(TW_CONTROL_UNMASK_COMMAND_INTERRUPT, TW_CONTROL_REG_AD…  argument
260 #define TW_SOFT_RESET(x) (outl(TW_CONTROL_ISSUE_SOFT_RESET | \  argument
266 			TW_CONTROL_DISABLE_INTERRUPTS, TW_CONTROL_REG_ADDR(x)))
267 #define TW_STATUS_ERRORS(x) \  argument
268 	(((x & TW_STATUS_PCI_ABORT) || \
269 	(x & TW_STATUS_PCI_PARITY_ERROR) || \
270 	(x & TW_STATUS_QUEUE_ERROR) || \
271 	(x & TW_STATUS_MICROCONTROLLER_ERROR)) && \
272 	(x & TW_STATUS_MICROCONTROLLER_READY))