414 	status = NCR5380_read(STATUS_REG);  in NCR5380_print()
455 	status = NCR5380_read(STATUS_REG);  in NCR5380_print_phase()
864 	for (pass = 1; (NCR5380_read(STATUS_REG) & SR_BSY) && pass <= 6; ++pass) {  in NCR5380_init()
871 			NCR5380_poll_politely(instance, STATUS_REG, SR_BSY, 0, 5*HZ);  in NCR5380_init()
1122 			if ((NCR5380_read(STATUS_REG) & (SR_SEL | SR_IO)) == (SR_SEL | SR_IO)) {  in NCR5380_intr()
1130 			} else if ((NCR5380_read(STATUS_REG) & SR_RST) == SR_RST) {  in NCR5380_intr()
1161 …interrupt, BASR 0x%X, MR 0x%X, SR 0x%x\n", basr, NCR5380_read(MODE_REG), NCR5380_read(STATUS_REG));  in NCR5380_intr()
1364 	value = NCR5380_read(STATUS_REG) & (SR_BSY | SR_IO);  in NCR5380_select()
1376 	if ((NCR5380_read(STATUS_REG) & (SR_SEL | SR_IO)) == (SR_SEL | SR_IO)) {  in NCR5380_select()
1393 	if (!(NCR5380_read(STATUS_REG) & SR_BSY)) {  in NCR5380_select()
1430 	err = NCR5380_poll_politely(instance, STATUS_REG, SR_REQ, SR_REQ, HZ);  in NCR5380_select()
1532 		while (!((tmp = NCR5380_read(STATUS_REG)) & SR_REQ) && !break_allowed);  in NCR5380_transfer_pio()
1578 		NCR5380_poll_politely(instance, STATUS_REG, SR_REQ, 0, 5*HZ);  in NCR5380_transfer_pio()
1604 	tmp = NCR5380_read(STATUS_REG);  in NCR5380_transfer_pio()
1630 	NCR5380_write(TARGET_COMMAND_REG, PHASE_SR_TO_TCR(NCR5380_read(STATUS_REG) & PHASE_MASK));  in do_reset()
1669 	rc = NCR5380_poll_politely(host, STATUS_REG, SR_REQ, SR_REQ, 60 * HZ);  in do_abort()
1680 		rc = NCR5380_poll_politely(host, STATUS_REG, SR_REQ, 0, 3*HZ);  in do_abort()
1737 	if ((tmp = (NCR5380_read(STATUS_REG) & PHASE_MASK)) != p) {  in NCR5380_transfer_dma()
1845 …while (((tmp = NCR5380_read(BUS_AND_STATUS_REG)) & BASR_ACK) || (NCR5380_read(STATUS_REG) & SR_REQ…  in NCR5380_transfer_dma()
1853 …ed DMA transfer complete, basr 0x%X, sr 0x%X\n", instance->host_no, tmp, NCR5380_read(STATUS_REG));  in NCR5380_transfer_dma()
1862 	*phase = NCR5380_read(STATUS_REG) & PHASE_MASK;  in NCR5380_transfer_dma()
1922 				while (NCR5380_read(STATUS_REG) & SR_REQ);  in NCR5380_transfer_dma()
1974 	*phase = NCR5380_read(STATUS_REG) & PHASE_MASK;  in NCR5380_transfer_dma()
2020 		tmp = NCR5380_read(STATUS_REG);
2032 				while (NCR5380_read(STATUS_REG) & SR_REQ);
2216 					while ((NCR5380_read(STATUS_REG) & SR_BSY) && !hostdata->connected)
2252 						while ((NCR5380_read(STATUS_REG) & SR_BSY) && !hostdata->connected)
2444 	if(NCR5380_poll_politely(instance, STATUS_REG, SR_SEL, 0, 2*HZ)<0)
2454 	if(NCR5380_poll_politely(instance, STATUS_REG, SR_REQ, SR_REQ, 2*HZ))
2596 …ABORT, "        basr 0x%X, sr 0x%X\n", NCR5380_read(BUS_AND_STATUS_REG), NCR5380_read(STATUS_REG));