484 	iowrite32(0xffff, mhba->ib_shadow);  in mvumi_send_ib_list_entry()
485 	iowrite32(mhba->ib_cur_slot, mhba->regs->inb_write_pointer);  in mvumi_send_ib_list_entry()
604 	iowrite32(mhba->ob_cur_slot, regs->outb_read_pointer);  in mvumi_receive_ob_list_entry()
611 	iowrite32(0, regs->enpointa_mask_reg);  in mvumi_reset()
615 	iowrite32(DRBL_SOFT_RESET, regs->pciea_to_arm_drbl_reg);  in mvumi_reset()
638 	iowrite32(0, regs->enpointa_mask_reg);  in mvumi_wait_for_fw()
641 		iowrite32(DRBL_MU_RESET, regs->pciea_to_arm_drbl_reg);  in mvumi_wait_for_fw()
695 	iowrite32(0, mhba->regs->reset_enable);  in mvumi_reset_host_9580()
696 	iowrite32(0xf, mhba->regs->reset_request);  in mvumi_reset_host_9580()
698 	iowrite32(0x10, mhba->regs->reset_enable);  in mvumi_reset_host_9580()
699 	iowrite32(0x10, mhba->regs->reset_request);  in mvumi_reset_host_9580()
1141 		iowrite32(HANDSHAKE_SIGNATURE, regs->pciea_to_arm_msg1);  in mvumi_handshake()
1142 		iowrite32(hs_fun, regs->pciea_to_arm_msg0);  in mvumi_handshake()
1143 		iowrite32(DRBL_HANDSHAKE, regs->pciea_to_arm_drbl_reg);  in mvumi_handshake()
1147 		iowrite32(lower_32_bits(mhba->handshake_page_phys),  in mvumi_handshake()
1149 		iowrite32(upper_32_bits(mhba->handshake_page_phys),  in mvumi_handshake()
1153 		iowrite32(hs_fun, regs->pciea_to_arm_msg0);  in mvumi_handshake()
1154 		iowrite32(DRBL_HANDSHAKE, regs->pciea_to_arm_drbl_reg);  in mvumi_handshake()
1194 		iowrite32(hs_fun, regs->pciea_to_arm_msg0);  in mvumi_handshake()
1195 		iowrite32(DRBL_HANDSHAKE, regs->pciea_to_arm_drbl_reg);  in mvumi_handshake()
1202 		iowrite32(tmp, regs->enpointa_mask_reg);  in mvumi_handshake()
1203 		iowrite32(mhba->list_num_io, mhba->ib_shadow);  in mvumi_handshake()
1205 		iowrite32(lower_32_bits(mhba->ib_shadow_phys),  in mvumi_handshake()
1207 		iowrite32(upper_32_bits(mhba->ib_shadow_phys),  in mvumi_handshake()
1212 			iowrite32((mhba->list_num_io-1) |  in mvumi_handshake()
1215 			iowrite32(lower_32_bits(mhba->ob_shadow_phys),  in mvumi_handshake()
1217 			iowrite32(upper_32_bits(mhba->ob_shadow_phys),  in mvumi_handshake()
1273 			iowrite32(DRBL_MU_RESET,  in mvumi_check_handshake()
1308 	iowrite32(tmp, regs->arm_to_pciea_drbl_reg);  in mvumi_start()
1310 	iowrite32(regs->int_drbl_int_mask, regs->arm_to_pciea_mask_reg);  in mvumi_start()
1312 	iowrite32(tmp, regs->enpointa_mask_reg);  in mvumi_start()
1940 	iowrite32(regs->int_drbl_int_mask, regs->arm_to_pciea_mask_reg);  in mvumi_enable_intr()
1943 	iowrite32(mask, regs->enpointa_mask_reg);  in mvumi_enable_intr()
1955 	iowrite32(0, regs->arm_to_pciea_mask_reg);  in mvumi_disable_intr()
1959 	iowrite32(mask, regs->enpointa_mask_reg);  in mvumi_disable_intr()
1975 				iowrite32(tmp & regs->clic_out_err,  in mvumi_clear_intr()
1980 				iowrite32(tmp & (regs->clic_in_err |  in mvumi_clear_intr()
1990 			iowrite32(tmp & regs->clic_irq, regs->outb_isr_cause);  in mvumi_clear_intr()
1995 			iowrite32(isr_status, regs->arm_to_pciea_drbl_reg);  in mvumi_clear_intr()
2014 		iowrite32(status, mhba->regs->arm_to_pciea_drbl_reg);  in mvumi_read_fw_status_reg()