306 #define NSP32_DEBUG_INTR		BIT(3)  macro
441 	nsp32_dbg(NSP32_DEBUG_INTR, "timer=%d", time);
444 		nsp32_dbg(NSP32_DEBUG_INTR, "timer set overflow");
1179 	nsp32_dbg(NSP32_DEBUG_INTR,   in do_nsp32_isr()
1183 		nsp32_dbg(NSP32_DEBUG_INTR, "shared interrupt: irq other 0x%x", irq_stat);  in do_nsp32_isr()
1205 		nsp32_dbg(NSP32_DEBUG_INTR, "timer stop");  in do_nsp32_isr()
1240 			nsp32_dbg(NSP32_DEBUG_INTR,  in do_nsp32_isr()
1265 			nsp32_dbg(NSP32_DEBUG_INTR, "MsgOut phase processed");  in do_nsp32_isr()
1277 			nsp32_dbg(NSP32_DEBUG_INTR,  in do_nsp32_isr()
1281 			nsp32_dbg(NSP32_DEBUG_INTR, "BMCNT=0x%lx",   in do_nsp32_isr()
1283 			nsp32_dbg(NSP32_DEBUG_INTR, "addr=0x%lx",   in do_nsp32_isr()
1285 			nsp32_dbg(NSP32_DEBUG_INTR, "SACK=0x%lx",   in do_nsp32_isr()
1287 			nsp32_dbg(NSP32_DEBUG_INTR, "SSACK=0x%lx",   in do_nsp32_isr()
1346 			nsp32_dbg(NSP32_DEBUG_INTR, "Command phase processed");  in do_nsp32_isr()
1358 		nsp32_dbg(NSP32_DEBUG_INTR, "FIFO IRQ");  in do_nsp32_isr()
1362 			nsp32_dbg(NSP32_DEBUG_INTR, "fifo/write");  in do_nsp32_isr()
1369 			nsp32_dbg(NSP32_DEBUG_INTR, "fifo/read");  in do_nsp32_isr()
1376 			nsp32_dbg(NSP32_DEBUG_INTR, "fifo/status");  in do_nsp32_isr()
1382 			nsp32_dbg(NSP32_DEBUG_INTR, "fifo/other phase");  in do_nsp32_isr()
1383 			nsp32_dbg(NSP32_DEBUG_INTR, "irq_stat=0x%x trans_stat=0x%x", irq_stat, trans_stat);  in do_nsp32_isr()
1393 		nsp32_dbg(NSP32_DEBUG_INTR, "phase change IRQ");  in do_nsp32_isr()
1397 			nsp32_dbg(NSP32_DEBUG_INTR, "phase chg/msg in");  in do_nsp32_isr()
1412 		nsp32_dbg(NSP32_DEBUG_INTR, "PCI IRQ occurred");  in do_nsp32_isr()
1427 	nsp32_dbg(NSP32_DEBUG_INTR,  in do_nsp32_isr()
1439 	nsp32_dbg(NSP32_DEBUG_INTR, "exit");  in do_nsp32_isr()