101 static volatile struct sun3_dma_regs *dregs;  variable
130 	dregs->udc_addr = UDC_CSR;  in sun3_udc_read()
132 	ret = dregs->udc_data;  in sun3_udc_read()
140 	dregs->udc_addr = reg;  in sun3_udc_write()
142 	dregs->udc_data = val;  in sun3_udc_write()
191 	unsigned short csr = dregs->csr;  in scsi_sun3_intr()
195 	dregs->csr &= ~CSR_DMA_ENABLE;  in scsi_sun3_intr()
255 	dregs->fifo_count = 0;  in sun3scsi_dma_setup()
259 	dregs->csr &= ~CSR_FIFO;  in sun3scsi_dma_setup()
260 	dregs->csr |= CSR_FIFO;  in sun3scsi_dma_setup()
265 		dregs->csr |= CSR_SEND;  in sun3scsi_dma_setup()
267 		dregs->csr &= ~CSR_SEND;  in sun3scsi_dma_setup()
270 	dregs->csr |= CSR_PACK_ENABLE;  in sun3scsi_dma_setup()
272 	dregs->dma_addr_hi = ((unsigned long)addr >> 16);  in sun3scsi_dma_setup()
273 	dregs->dma_addr_lo = ((unsigned long)addr & 0xffff);  in sun3scsi_dma_setup()
275 	dregs->dma_count_hi = 0;  in sun3scsi_dma_setup()
276 	dregs->dma_count_lo = 0;  in sun3scsi_dma_setup()
277 	dregs->fifo_count_hi = 0;  in sun3scsi_dma_setup()
278 	dregs->fifo_count = 0;  in sun3scsi_dma_setup()
281 	dregs->fifo_count = count;  in sun3scsi_dma_setup()
286 	dregs->csr &= ~CSR_FIFO;  in sun3scsi_dma_setup()
287 	dregs->csr |= CSR_FIFO;  in sun3scsi_dma_setup()
289 	if(dregs->fifo_count != count) {   in sun3scsi_dma_setup()
291 		       default_instance->host_no, dregs->fifo_count,  in sun3scsi_dma_setup()
333 	dregs->udc_addr = 0x32;   in sun3scsi_dma_count()
335 	resid = dregs->udc_data;  in sun3scsi_dma_count()
363 	csr = dregs->csr;  in sun3scsi_dma_start()
365 	dregs->dma_count_hi = (sun3_dma_orig_count >> 16);  in sun3scsi_dma_start()
366 	dregs->dma_count_lo = (sun3_dma_orig_count & 0xffff);  in sun3scsi_dma_start()
368 	dregs->fifo_count_hi = (sun3_dma_orig_count >> 16);  in sun3scsi_dma_start()
369 	dregs->fifo_count = (sun3_dma_orig_count & 0xffff);  in sun3scsi_dma_start()
391 	dregs->csr &= ~CSR_DMA_ENABLE;  in sun3scsi_dma_finish()
393 	fifo = dregs->fifo_count;  in sun3scsi_dma_finish()
401 	if ((!write_flag) && (dregs->csr & CSR_LEFT)) {  in sun3scsi_dma_finish()
409 		switch (dregs->csr & CSR_LEFT) {  in sun3scsi_dma_finish()
411 			*vaddr = (dregs->bpack_lo & 0xff00) >> 8;  in sun3scsi_dma_finish()
415 			*vaddr = (dregs->bpack_hi & 0x00ff);  in sun3scsi_dma_finish()
419 			*vaddr = (dregs->bpack_hi & 0xff00) >> 8;  in sun3scsi_dma_finish()
429 			if(dregs->csr & CSR_FIFO_EMPTY)  in sun3scsi_dma_finish()
442 	fifo = dregs->fifo_count;  in sun3scsi_dma_finish()
450 		data = dregs->fifo_data;  in sun3scsi_dma_finish()
464 	dregs->dma_addr_hi = 0;  in sun3scsi_dma_finish()
465 	dregs->dma_addr_lo = 0;  in sun3scsi_dma_finish()
466 	dregs->dma_count_hi = 0;  in sun3scsi_dma_finish()
467 	dregs->dma_count_lo = 0;  in sun3scsi_dma_finish()
469 	dregs->fifo_count = 0;  in sun3scsi_dma_finish()
470 	dregs->fifo_count_hi = 0;  in sun3scsi_dma_finish()
472 	dregs->csr &= ~CSR_SEND;  in sun3scsi_dma_finish()
476 	dregs->fifo_count = 0;  in sun3scsi_dma_finish()
477 	dregs->csr &= ~CSR_SEND;  in sun3scsi_dma_finish()
480 	dregs->csr &= ~CSR_FIFO;  in sun3scsi_dma_finish()
481 	dregs->csr |= CSR_FIFO;  in sun3scsi_dma_finish()
550 		dregs = (struct sun3_dma_regs *)(ioaddr + 8);  in sun3_scsi_probe()
552 		if (sun3_map_test((unsigned long)dregs, &x)) {  in sun3_scsi_probe()
555 			oldcsr = dregs->csr;  in sun3_scsi_probe()
556 			dregs->csr = 0;  in sun3_scsi_probe()
558 			if (dregs->csr == 0x1400)  in sun3_scsi_probe()
561 			dregs->csr = oldcsr;  in sun3_scsi_probe()
576 	dregs = (struct sun3_dma_regs *)(ioaddr + 8);  in sun3_scsi_probe()
619 	dregs->csr = 0;  in sun3_scsi_probe()
621 	dregs->csr = CSR_SCSI | CSR_FIFO | CSR_INTR;  in sun3_scsi_probe()
623 	dregs->fifo_count = 0;  in sun3_scsi_probe()
625 	dregs->fifo_count_hi = 0;  in sun3_scsi_probe()
626 	dregs->dma_addr_hi = 0;  in sun3_scsi_probe()
627 	dregs->dma_addr_lo = 0;  in sun3_scsi_probe()
628 	dregs->dma_count_hi = 0;  in sun3_scsi_probe()
629 	dregs->dma_count_lo = 0;  in sun3_scsi_probe()
631 	dregs->ivect = VME_DATA24 | (instance->irq & 0xff);  in sun3_scsi_probe()