354 	ufshcd_writel(hba, ~(1 << pos), REG_UTP_TRANSFER_REQ_LIST_CLEAR);  in ufshcd_utrl_clear()
463 	ufshcd_writel(hba, INT_AGGR_ENABLE |  in ufshcd_reset_intr_aggr()
477 	ufshcd_writel(hba, INT_AGGR_ENABLE | INT_AGGR_PARAM_WRITE |  in ufshcd_config_intr_aggr()
491 	ufshcd_writel(hba, UTP_TASK_REQ_LIST_RUN_STOP_BIT,  in ufshcd_enable_run_stop_reg()
493 	ufshcd_writel(hba, UTP_TRANSFER_REQ_LIST_RUN_STOP_BIT,  in ufshcd_enable_run_stop_reg()
503 	ufshcd_writel(hba, CONTROLLER_ENABLE, REG_CONTROLLER_ENABLE);  in ufshcd_hba_start()
788 	ufshcd_writel(hba, 1 << task_tag, REG_UTP_TRANSFER_REQ_DOOR_BELL);  in ufshcd_send_command()
900 	ufshcd_writel(hba, uic_cmd->argument1, REG_UIC_COMMAND_ARG_1);  in ufshcd_dispatch_uic_cmd()
901 	ufshcd_writel(hba, uic_cmd->argument2, REG_UIC_COMMAND_ARG_2);  in ufshcd_dispatch_uic_cmd()
902 	ufshcd_writel(hba, uic_cmd->argument3, REG_UIC_COMMAND_ARG_3);  in ufshcd_dispatch_uic_cmd()
905 	ufshcd_writel(hba, uic_cmd->command & COMMAND_OPCODE_MASK,  in ufshcd_dispatch_uic_cmd()
1047 	ufshcd_writel(hba, set, REG_INTERRUPT_ENABLE);  in ufshcd_enable_intr()
1069 	ufshcd_writel(hba, set, REG_INTERRUPT_ENABLE);  in ufshcd_disable_intr()
2528 	ufshcd_writel(hba, lower_32_bits(hba->utrdl_dma_addr),  in ufshcd_make_hba_operational()
2530 	ufshcd_writel(hba, upper_32_bits(hba->utrdl_dma_addr),  in ufshcd_make_hba_operational()
2532 	ufshcd_writel(hba, lower_32_bits(hba->utmrdl_dma_addr),  in ufshcd_make_hba_operational()
2534 	ufshcd_writel(hba, upper_32_bits(hba->utmrdl_dma_addr),  in ufshcd_make_hba_operational()
3560 		ufshcd_writel(hba, intr_status, REG_INTERRUPT_STATUS);  in ufshcd_intr()
3578 	ufshcd_writel(hba, ~(1 << tag), REG_UTP_TASK_REQ_LIST_CLEAR);  in ufshcd_clear_tm_cmd()
3647 	ufshcd_writel(hba, 1 << free_slot, REG_UTP_TASK_REQ_DOOR_BELL);  in ufshcd_issue_tm_cmd()