166 static void tegra_pmc_writel(u32 value, unsigned long offset)  in tegra_pmc_writel()  argument
168 	writel(value, pmc->base + offset);  in tegra_pmc_writel()
387 	u32 value;  in tegra_pmc_restart()  local
389 	value = tegra_pmc_readl(PMC_SCRATCH0);  in tegra_pmc_restart()
390 	value &= ~PMC_SCRATCH0_MODE_MASK;  in tegra_pmc_restart()
394 			value |= PMC_SCRATCH0_MODE_RECOVERY;  in tegra_pmc_restart()
397 			value |= PMC_SCRATCH0_MODE_BOOTLOADER;  in tegra_pmc_restart()
400 			value |= PMC_SCRATCH0_MODE_RCM;  in tegra_pmc_restart()
403 	tegra_pmc_writel(value, PMC_SCRATCH0);  in tegra_pmc_restart()
405 	value = tegra_pmc_readl(0);  in tegra_pmc_restart()
406 	value |= 0x10;  in tegra_pmc_restart()
407 	tegra_pmc_writel(value, 0);  in tegra_pmc_restart()
455 	unsigned long rate, value;  in tegra_io_rail_prepare()  local
485 	value = DIV_ROUND_UP(1000000000, rate);  in tegra_io_rail_prepare()
486 	value = DIV_ROUND_UP(200, value);  in tegra_io_rail_prepare()
487 	tegra_pmc_writel(value, SEL_DPD_TIM);  in tegra_io_rail_prepare()
495 	unsigned long value;  in tegra_io_rail_poll()  local
500 		value = tegra_pmc_readl(offset);  in tegra_io_rail_poll()
501 		if ((value & mask) == val)  in tegra_io_rail_poll()
517 	unsigned long request, status, value;  in tegra_io_rail_power_on()  local
527 	value = tegra_pmc_readl(request);  in tegra_io_rail_power_on()
528 	value |= mask;  in tegra_io_rail_power_on()
529 	value &= ~IO_DPD_REQ_CODE_MASK;  in tegra_io_rail_power_on()
530 	value |= IO_DPD_REQ_CODE_OFF;  in tegra_io_rail_power_on()
531 	tegra_pmc_writel(value, request);  in tegra_io_rail_power_on()
545 	unsigned long request, status, value;  in tegra_io_rail_power_off()  local
555 	value = tegra_pmc_readl(request);  in tegra_io_rail_power_off()
556 	value |= mask;  in tegra_io_rail_power_off()
557 	value &= ~IO_DPD_REQ_CODE_MASK;  in tegra_io_rail_power_off()
558 	value |= IO_DPD_REQ_CODE_ON;  in tegra_io_rail_power_off()
559 	tegra_pmc_writel(value, request);  in tegra_io_rail_power_off()
588 	u32 value;  in tegra_pmc_enter_suspend_mode()  local
622 	value = tegra_pmc_readl(PMC_CNTRL);  in tegra_pmc_enter_suspend_mode()
623 	value &= ~PMC_CNTRL_SIDE_EFFECT_LP0;  in tegra_pmc_enter_suspend_mode()
624 	value |= PMC_CNTRL_CPU_PWRREQ_OE;  in tegra_pmc_enter_suspend_mode()
625 	tegra_pmc_writel(value, PMC_CNTRL);  in tegra_pmc_enter_suspend_mode()
631 	u32 value, values[2];  in tegra_pmc_parse_dt()  local
633 	if (of_property_read_u32(np, "nvidia,suspend-mode", &value)) {  in tegra_pmc_parse_dt()
635 		switch (value) {  in tegra_pmc_parse_dt()
656 	if (of_property_read_u32(np, "nvidia,cpu-pwr-good-time", &value))  in tegra_pmc_parse_dt()
659 	pmc->cpu_good_time = value;  in tegra_pmc_parse_dt()
661 	if (of_property_read_u32(np, "nvidia,cpu-pwr-off-time", &value))  in tegra_pmc_parse_dt()
664 	pmc->cpu_off_time = value;  in tegra_pmc_parse_dt()
673 	if (of_property_read_u32(np, "nvidia,core-pwr-off-time", &value))  in tegra_pmc_parse_dt()
676 	pmc->core_off_time = value;  in tegra_pmc_parse_dt()
703 	u32 value;  in tegra_pmc_init()  local
706 	value = tegra_pmc_readl(PMC_CNTRL);  in tegra_pmc_init()
707 	value |= PMC_CNTRL_CPU_PWRREQ_OE;  in tegra_pmc_init()
708 	tegra_pmc_writel(value, PMC_CNTRL);  in tegra_pmc_init()
710 	value = tegra_pmc_readl(PMC_CNTRL);  in tegra_pmc_init()
713 		value &= ~PMC_CNTRL_SYSCLK_POLARITY;  in tegra_pmc_init()
715 		value |= PMC_CNTRL_SYSCLK_POLARITY;  in tegra_pmc_init()
718 	tegra_pmc_writel(value, PMC_CNTRL);  in tegra_pmc_init()
721 	value = tegra_pmc_readl(PMC_CNTRL);  in tegra_pmc_init()
722 	value |= PMC_CNTRL_SYSCLK_OE;  in tegra_pmc_init()
723 	tegra_pmc_writel(value, PMC_CNTRL);  in tegra_pmc_init()
732 	u32 value, checksum;  in tegra_pmc_init_tsense_reset()  local
766 	value = tegra_pmc_readl(PMC_SENSOR_CTRL);  in tegra_pmc_init_tsense_reset()
767 	value |= PMC_SENSOR_CTRL_SCRATCH_WRITE;  in tegra_pmc_init_tsense_reset()
768 	tegra_pmc_writel(value, PMC_SENSOR_CTRL);  in tegra_pmc_init_tsense_reset()
770 	value = (reg_data << PMC_SCRATCH54_DATA_SHIFT) |  in tegra_pmc_init_tsense_reset()
772 	tegra_pmc_writel(value, PMC_SCRATCH54);  in tegra_pmc_init_tsense_reset()
774 	value = PMC_SCRATCH55_RESET_TEGRA;  in tegra_pmc_init_tsense_reset()
775 	value |= ctrl_id << PMC_SCRATCH55_CNTRL_ID_SHIFT;  in tegra_pmc_init_tsense_reset()
776 	value |= pinmux << PMC_SCRATCH55_PINMUX_SHIFT;  in tegra_pmc_init_tsense_reset()
777 	value |= pmu_addr << PMC_SCRATCH55_I2CSLV1_SHIFT;  in tegra_pmc_init_tsense_reset()
783 	checksum = reg_addr + reg_data + (value & 0xff) + ((value >> 8) & 0xff)  in tegra_pmc_init_tsense_reset()
784 		+ ((value >> 24) & 0xff);  in tegra_pmc_init_tsense_reset()
788 	value |= checksum << PMC_SCRATCH55_CHECKSUM_SHIFT;  in tegra_pmc_init_tsense_reset()
790 	tegra_pmc_writel(value, PMC_SCRATCH55);  in tegra_pmc_init_tsense_reset()
792 	value = tegra_pmc_readl(PMC_SENSOR_CTRL);  in tegra_pmc_init_tsense_reset()
793 	value |= PMC_SENSOR_CTRL_ENABLE_RST;  in tegra_pmc_init_tsense_reset()
794 	tegra_pmc_writel(value, PMC_SENSOR_CTRL);  in tegra_pmc_init_tsense_reset()
1025 	u32 value;  in tegra_pmc_early_init()  local
1058 	value = tegra_pmc_readl(PMC_CNTRL);  in tegra_pmc_early_init()
1061 		value |= PMC_CNTRL_INTR_POLARITY;  in tegra_pmc_early_init()
1063 		value &= ~PMC_CNTRL_INTR_POLARITY;  in tegra_pmc_early_init()
1065 	tegra_pmc_writel(value, PMC_CNTRL);  in tegra_pmc_early_init()