52 #define SSP_WRITE_BITS(reg, val, mask, sb) \  macro
1959 		SSP_WRITE_BITS(chip->dmacr, SSP_DMA_ENABLED,  in pl022_setup()
1961 		SSP_WRITE_BITS(chip->dmacr, SSP_DMA_ENABLED,  in pl022_setup()
1966 		SSP_WRITE_BITS(chip->dmacr, SSP_DMA_DISABLED,  in pl022_setup()
1968 		SSP_WRITE_BITS(chip->dmacr, SSP_DMA_DISABLED,  in pl022_setup()
1980 			SSP_WRITE_BITS(chip->cr1, chip_info->clkdelay,  in pl022_setup()
1984 			SSP_WRITE_BITS(chip->cr0, chip_info->duplex,  in pl022_setup()
1986 			SSP_WRITE_BITS(chip->cr0, chip_info->ctrl_len,  in pl022_setup()
1988 			SSP_WRITE_BITS(chip->cr0, chip_info->iface,  in pl022_setup()
1990 			SSP_WRITE_BITS(chip->cr1, chip_info->wait_state,  in pl022_setup()
1993 		SSP_WRITE_BITS(chip->cr0, bits - 1,  in pl022_setup()
2003 		SSP_WRITE_BITS(chip->cr1, tmp, SSP_CR1_MASK_RENDN_ST, 4);  in pl022_setup()
2004 		SSP_WRITE_BITS(chip->cr1, etx, SSP_CR1_MASK_TENDN_ST, 5);  in pl022_setup()
2005 		SSP_WRITE_BITS(chip->cr1, chip_info->rx_lev_trig,  in pl022_setup()
2007 		SSP_WRITE_BITS(chip->cr1, chip_info->tx_lev_trig,  in pl022_setup()
2010 		SSP_WRITE_BITS(chip->cr0, bits - 1,  in pl022_setup()
2012 		SSP_WRITE_BITS(chip->cr0, chip_info->iface,  in pl022_setup()
2021 	SSP_WRITE_BITS(chip->cr0, tmp, SSP_CR0_MASK_SPO, 6);  in pl022_setup()
2027 	SSP_WRITE_BITS(chip->cr0, tmp, SSP_CR0_MASK_SPH, 7);  in pl022_setup()
2029 	SSP_WRITE_BITS(chip->cr0, clk_freq.scr, SSP_CR0_MASK_SCR, 8);  in pl022_setup()
2036 		SSP_WRITE_BITS(chip->cr1, tmp, SSP_CR1_MASK_LBM, 0);  in pl022_setup()
2038 	SSP_WRITE_BITS(chip->cr1, SSP_DISABLED, SSP_CR1_MASK_SSE, 1);  in pl022_setup()
2039 	SSP_WRITE_BITS(chip->cr1, chip_info->hierarchy, SSP_CR1_MASK_MS, 2);  in pl022_setup()
2040 	SSP_WRITE_BITS(chip->cr1, chip_info->slave_tx_disable, SSP_CR1_MASK_SOD,  in pl022_setup()