203 	writel(data, sspi->base + SIRFSOC_SPI_TXFIFO_DATA);  in spi_sirfsoc_tx_word_u8()
232 	writel(data, sspi->base + SIRFSOC_SPI_TXFIFO_DATA);  in spi_sirfsoc_tx_word_u16()
262 	writel(data, sspi->base + SIRFSOC_SPI_TXFIFO_DATA);  in spi_sirfsoc_tx_word_u32()
272 		writel(0x0, sspi->base + SIRFSOC_SPI_INT_EN);  in spi_sirfsoc_irq()
273 		writel(SIRFSOC_SPI_INT_MASK_ALL,  in spi_sirfsoc_irq()
283 		writel(0x0, sspi->base + SIRFSOC_SPI_INT_EN);  in spi_sirfsoc_irq()
284 		writel(SIRFSOC_SPI_INT_MASK_ALL,  in spi_sirfsoc_irq()
294 	writel(0x0, sspi->base + SIRFSOC_SPI_INT_EN);  in spi_sirfsoc_irq()
295 	writel(SIRFSOC_SPI_INT_MASK_ALL,  in spi_sirfsoc_irq()
316 	writel(SIRFSOC_SPI_FIFO_RESET, sspi->base + SIRFSOC_SPI_TXFIFO_OP);  in spi_sirfsoc_cmd_transfer()
317 	writel(SIRFSOC_SPI_FIFO_START, sspi->base + SIRFSOC_SPI_TXFIFO_OP);  in spi_sirfsoc_cmd_transfer()
325 	writel(cmd, sspi->base + SIRFSOC_SPI_CMD);  in spi_sirfsoc_cmd_transfer()
326 	writel(SIRFSOC_SPI_FRM_END_INT_EN,  in spi_sirfsoc_cmd_transfer()
328 	writel(SIRFSOC_SPI_CMD_TX_EN,  in spi_sirfsoc_cmd_transfer()
345 	writel(SIRFSOC_SPI_FIFO_RESET, sspi->base + SIRFSOC_SPI_RXFIFO_OP);  in spi_sirfsoc_dma_transfer()
346 	writel(SIRFSOC_SPI_FIFO_RESET, sspi->base + SIRFSOC_SPI_TXFIFO_OP);  in spi_sirfsoc_dma_transfer()
347 	writel(SIRFSOC_SPI_FIFO_START, sspi->base + SIRFSOC_SPI_RXFIFO_OP);  in spi_sirfsoc_dma_transfer()
348 	writel(SIRFSOC_SPI_FIFO_START, sspi->base + SIRFSOC_SPI_TXFIFO_OP);  in spi_sirfsoc_dma_transfer()
349 	writel(0, sspi->base + SIRFSOC_SPI_INT_EN);  in spi_sirfsoc_dma_transfer()
350 	writel(SIRFSOC_SPI_INT_MASK_ALL, sspi->base + SIRFSOC_SPI_INT_STATUS);  in spi_sirfsoc_dma_transfer()
352 		writel(readl(sspi->base + SIRFSOC_SPI_CTRL) |  in spi_sirfsoc_dma_transfer()
355 		writel(sspi->left_tx_word - 1,  in spi_sirfsoc_dma_transfer()
357 		writel(sspi->left_tx_word - 1,  in spi_sirfsoc_dma_transfer()
360 		writel(readl(sspi->base + SIRFSOC_SPI_CTRL),  in spi_sirfsoc_dma_transfer()
362 		writel(0, sspi->base + SIRFSOC_SPI_TX_DMA_IO_LEN);  in spi_sirfsoc_dma_transfer()
363 		writel(0, sspi->base + SIRFSOC_SPI_RX_DMA_IO_LEN);  in spi_sirfsoc_dma_transfer()
387 	writel(SIRFSOC_SPI_RX_EN | SIRFSOC_SPI_TX_EN,  in spi_sirfsoc_dma_transfer()
406 	writel(0, sspi->base + SIRFSOC_SPI_RXFIFO_OP);  in spi_sirfsoc_dma_transfer()
407 	writel(0, sspi->base + SIRFSOC_SPI_TXFIFO_OP);  in spi_sirfsoc_dma_transfer()
409 		writel(0, sspi->base + SIRFSOC_SPI_TX_RX_EN);  in spi_sirfsoc_dma_transfer()
420 		writel(SIRFSOC_SPI_FIFO_RESET,  in spi_sirfsoc_pio_transfer()
422 		writel(SIRFSOC_SPI_FIFO_RESET,  in spi_sirfsoc_pio_transfer()
424 		writel(SIRFSOC_SPI_FIFO_START,  in spi_sirfsoc_pio_transfer()
426 		writel(SIRFSOC_SPI_FIFO_START,  in spi_sirfsoc_pio_transfer()
428 		writel(0, sspi->base + SIRFSOC_SPI_INT_EN);  in spi_sirfsoc_pio_transfer()
429 		writel(SIRFSOC_SPI_INT_MASK_ALL,  in spi_sirfsoc_pio_transfer()
431 		writel(readl(sspi->base + SIRFSOC_SPI_CTRL) |  in spi_sirfsoc_pio_transfer()
434 		writel(min(sspi->left_tx_word, (u32)(256 / sspi->word_width))  in spi_sirfsoc_pio_transfer()
436 		writel(min(sspi->left_rx_word, (u32)(256 / sspi->word_width))  in spi_sirfsoc_pio_transfer()
441 		writel(SIRFSOC_SPI_TXFIFO_EMPTY_INT_EN |  in spi_sirfsoc_pio_transfer()
446 		writel(SIRFSOC_SPI_RX_EN | SIRFSOC_SPI_TX_EN,  in spi_sirfsoc_pio_transfer()
456 		writel(0, sspi->base + SIRFSOC_SPI_RXFIFO_OP);  in spi_sirfsoc_pio_transfer()
457 		writel(0, sspi->base + SIRFSOC_SPI_TXFIFO_OP);  in spi_sirfsoc_pio_transfer()
506 		writel(regval, sspi->base + SIRFSOC_SPI_CTRL);  in spi_sirfsoc_chipselect()
588 	writel(SIRFSOC_SPI_FIFO_SC(fifo_size - 2) |  in spi_sirfsoc_setup_transfer()
592 	writel(SIRFSOC_SPI_FIFO_SC(2) |  in spi_sirfsoc_setup_transfer()
596 	writel(txfifo_ctrl, sspi->base + SIRFSOC_SPI_TXFIFO_CTRL);  in spi_sirfsoc_setup_transfer()
597 	writel(rxfifo_ctrl, sspi->base + SIRFSOC_SPI_RXFIFO_CTRL);  in spi_sirfsoc_setup_transfer()
612 	writel(regval, sspi->base + SIRFSOC_SPI_CTRL);  in spi_sirfsoc_setup_transfer()
616 		writel(0, sspi->base + SIRFSOC_SPI_TX_DMA_IO_CTRL);  in spi_sirfsoc_setup_transfer()
617 		writel(SIRFSOC_SPI_RX_DMA_FLUSH,  in spi_sirfsoc_setup_transfer()
621 		writel(SIRFSOC_SPI_IO_MODE_SEL,  in spi_sirfsoc_setup_transfer()
623 		writel(SIRFSOC_SPI_IO_MODE_SEL,  in spi_sirfsoc_setup_transfer()
719 	writel(SIRFSOC_SPI_FIFO_RESET, sspi->base + SIRFSOC_SPI_RXFIFO_OP);  in spi_sirfsoc_probe()
720 	writel(SIRFSOC_SPI_FIFO_RESET, sspi->base + SIRFSOC_SPI_TXFIFO_OP);  in spi_sirfsoc_probe()
721 	writel(SIRFSOC_SPI_FIFO_START, sspi->base + SIRFSOC_SPI_RXFIFO_OP);  in spi_sirfsoc_probe()
722 	writel(SIRFSOC_SPI_FIFO_START, sspi->base + SIRFSOC_SPI_TXFIFO_OP);  in spi_sirfsoc_probe()
724 	writel(0, sspi->base + SIRFSOC_SPI_DUMMY_DELAY_CTL);  in spi_sirfsoc_probe()
807 	writel(SIRFSOC_SPI_FIFO_RESET, sspi->base + SIRFSOC_SPI_RXFIFO_OP);  in spi_sirfsoc_resume()
808 	writel(SIRFSOC_SPI_FIFO_RESET, sspi->base + SIRFSOC_SPI_TXFIFO_OP);  in spi_sirfsoc_resume()
809 	writel(SIRFSOC_SPI_FIFO_START, sspi->base + SIRFSOC_SPI_RXFIFO_OP);  in spi_sirfsoc_resume()
810 	writel(SIRFSOC_SPI_FIFO_START, sspi->base + SIRFSOC_SPI_TXFIFO_OP);  in spi_sirfsoc_resume()