Lines Matching refs:sOutW
1902 sOutW((WordIO_t) io + _INDX_ADDR, _CLK_PRE); /* clock prescaler */ in sPCIInitController()
2644 sOutW((WordIO_t) io + _INDX_ADDR, _CLK_PRE); /* clock prescaler */ in sInitController()
2701 sOutW(io + _INDX_ADDR, 0); /* read from SRAM, chan 0 */ in sReadAiopNumChan()
2703 sOutW(io + _INDX_ADDR, 0x4000); /* read from SRAM, chan 4 */ in sReadAiopNumChan()
2832 sOutW((WordIO_t) ChP->IndexAddr, ChP->TxFIFOPtrs); /* clear Tx in/out ptrs */ in sInitChan()
2833 sOutW(ChP->IndexData, 0); in sInitChan()
2839 sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs); /* clear Rx out ptr */ in sInitChan()
2840 sOutW(ChP->IndexData, 0); in sInitChan()
2841 sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs + 2); /* clear Rx in ptr */ in sInitChan()
2842 sOutW(ChP->IndexData, 0); in sInitChan()
2844 sOutW((WordIO_t) ChP->IndexAddr, ChP->TxPrioCnt); in sInitChan()
2847 sOutW((WordIO_t) ChP->IndexAddr, ChP->TxPrioPtr); in sInitChan()
2918 sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs); /* clear Rx out ptr */ in sFlushRxFIFO()
2919 sOutW(ChP->IndexData, 0); in sFlushRxFIFO()
2920 sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs + 2); /* clear Rx in ptr */ in sFlushRxFIFO()
2921 sOutW(ChP->IndexData, 0); in sFlushRxFIFO()
2960 sOutW((WordIO_t) ChP->IndexAddr, ChP->TxFIFOPtrs); /* clear Tx in/out ptrs */ in sFlushTxFIFO()
2961 sOutW(ChP->IndexData, 0); in sFlushTxFIFO()
2988 sOutW((WordIO_t) IndexAddr, ChP->TxPrioCnt); /* get priority buffer status */ in sWriteTxPrioByte()