Lines Matching refs:UART010_CR
82 cr = readb(uap->port.membase + UART010_CR); in pl010_stop_tx()
84 writel(cr, uap->port.membase + UART010_CR); in pl010_stop_tx()
93 cr = readb(uap->port.membase + UART010_CR); in pl010_start_tx()
95 writel(cr, uap->port.membase + UART010_CR); in pl010_start_tx()
104 cr = readb(uap->port.membase + UART010_CR); in pl010_stop_rx()
106 writel(cr, uap->port.membase + UART010_CR); in pl010_stop_rx()
114 cr = readb(uap->port.membase + UART010_CR); in pl010_disable_ms()
116 writel(cr, uap->port.membase + UART010_CR); in pl010_disable_ms()
125 cr = readb(uap->port.membase + UART010_CR); in pl010_enable_ms()
127 writel(cr, uap->port.membase + UART010_CR); in pl010_enable_ms()
357 uap->port.membase + UART010_CR); in pl010_startup()
380 writel(0, uap->port.membase + UART010_CR); in pl010_shutdown()
469 old_cr = readb(uap->port.membase + UART010_CR) & ~UART010_CR_MSIE; in pl010_set_termios()
474 writel(0, uap->port.membase + UART010_CR); in pl010_set_termios()
487 writel(old_cr, uap->port.membase + UART010_CR); in pl010_set_termios()
605 old_cr = readb(uap->port.membase + UART010_CR); in pl010_console_write()
606 writel(UART01x_CR_UARTEN, uap->port.membase + UART010_CR); in pl010_console_write()
618 writel(old_cr, uap->port.membase + UART010_CR); in pl010_console_write()
627 if (readb(uap->port.membase + UART010_CR) & UART01x_CR_UARTEN) { in pl010_console_get_options()