188 #define SER_RXD_MASK         IO_MASK(R_SERIAL0_STATUS, rxd)
189 #define SER_DATA_AVAIL_MASK  IO_MASK(R_SERIAL0_STATUS, data_avail)
190 #define SER_FRAMING_ERR_MASK IO_MASK(R_SERIAL0_STATUS, framing_err)
191 #define SER_PAR_ERR_MASK     IO_MASK(R_SERIAL0_STATUS, par_err)
192 #define SER_OVERRUN_MASK     IO_MASK(R_SERIAL0_STATUS, overrun)
218 | IO_MASK(R_IRQ_MASK1_RD, ser0_data) | IO_MASK(R_IRQ_MASK1_RD, ser0_ready)
221 | IO_MASK(R_IRQ_MASK1_RD, ser1_data) | IO_MASK(R_IRQ_MASK1_RD, ser1_ready)
224 | IO_MASK(R_IRQ_MASK1_RD, ser2_data) | IO_MASK(R_IRQ_MASK1_RD, ser2_ready)
227 | IO_MASK(R_IRQ_MASK1_RD, ser3_data) | IO_MASK(R_IRQ_MASK1_RD, ser3_ready)
1117 		(info->rx_ctrl &= ~IO_MASK(R_SERIAL0_REC_CTRL, rec_enable));  in e100_disable_rx()
1125 		(info->rx_ctrl |= IO_MASK(R_SERIAL0_REC_CTRL, rec_enable));  in e100_enable_rx()
1180 		if ((genconfig_shadow & IO_MASK(R_GEN_CONFIG, dma6)) ==  in e100_disable_txdma_channel()
1182 			genconfig_shadow &=  ~IO_MASK(R_GEN_CONFIG, dma6);  in e100_disable_txdma_channel()
1186 		if ((genconfig_shadow & IO_MASK(R_GEN_CONFIG, dma8)) ==  in e100_disable_txdma_channel()
1188 			genconfig_shadow &=  ~IO_MASK(R_GEN_CONFIG, dma8);  in e100_disable_txdma_channel()
1192 		if ((genconfig_shadow & IO_MASK(R_GEN_CONFIG, dma2)) ==  in e100_disable_txdma_channel()
1194 			genconfig_shadow &=  ~IO_MASK(R_GEN_CONFIG, dma2);  in e100_disable_txdma_channel()
1198 		if ((genconfig_shadow & IO_MASK(R_GEN_CONFIG, dma4)) ==  in e100_disable_txdma_channel()
1200 			genconfig_shadow &=  ~IO_MASK(R_GEN_CONFIG, dma4);  in e100_disable_txdma_channel()
1217 		genconfig_shadow &=  ~IO_MASK(R_GEN_CONFIG, dma6);  in e100_enable_txdma_channel()
1220 		genconfig_shadow &=  ~IO_MASK(R_GEN_CONFIG, dma8);  in e100_enable_txdma_channel()
1223 		genconfig_shadow &=  ~IO_MASK(R_GEN_CONFIG, dma2);  in e100_enable_txdma_channel()
1226 		genconfig_shadow &=  ~IO_MASK(R_GEN_CONFIG, dma4);  in e100_enable_txdma_channel()
1242 		if ((genconfig_shadow & IO_MASK(R_GEN_CONFIG, dma7)) ==  in e100_disable_rxdma_channel()
1244 			genconfig_shadow &=  ~IO_MASK(R_GEN_CONFIG, dma7);  in e100_disable_rxdma_channel()
1248 		if ((genconfig_shadow & IO_MASK(R_GEN_CONFIG, dma9)) ==  in e100_disable_rxdma_channel()
1250 			genconfig_shadow &=  ~IO_MASK(R_GEN_CONFIG, dma9);  in e100_disable_rxdma_channel()
1254 		if ((genconfig_shadow & IO_MASK(R_GEN_CONFIG, dma3)) ==  in e100_disable_rxdma_channel()
1256 			genconfig_shadow &=  ~IO_MASK(R_GEN_CONFIG, dma3);  in e100_disable_rxdma_channel()
1260 		if ((genconfig_shadow & IO_MASK(R_GEN_CONFIG, dma5)) ==  in e100_disable_rxdma_channel()
1262 			genconfig_shadow &=  ~IO_MASK(R_GEN_CONFIG, dma5);  in e100_disable_rxdma_channel()
1278 		genconfig_shadow &=  ~IO_MASK(R_GEN_CONFIG, dma7);  in e100_enable_rxdma_channel()
1281 		genconfig_shadow &=  ~IO_MASK(R_GEN_CONFIG, dma9);  in e100_enable_rxdma_channel()
1284 		genconfig_shadow &=  ~IO_MASK(R_GEN_CONFIG, dma3);  in e100_enable_rxdma_channel()
1287 		genconfig_shadow &=  ~IO_MASK(R_GEN_CONFIG, dma5);  in e100_enable_rxdma_channel()
1834 	if (rstat & IO_MASK(R_SERIAL0_STATUS, xoff_detect) ) {  in receive_chars_dma()
2197 	if (data_read & IO_MASK(R_SERIAL0_READ, xoff_detect) ) {  in handle_ser_rx_interrupt_no_dma()
2202 	if (data_read & ( IO_MASK(R_SERIAL0_READ, framing_err) |  in handle_ser_rx_interrupt_no_dma()
2203 			  IO_MASK(R_SERIAL0_READ, par_err) |  in handle_ser_rx_interrupt_no_dma()
2204 			  IO_MASK(R_SERIAL0_READ, overrun) )) {  in handle_ser_rx_interrupt_no_dma()
2217 		if ( ((data_read & IO_MASK(R_SERIAL0_READ, data_in)) == 0) &&  in handle_ser_rx_interrupt_no_dma()
2218 		     (data_read & IO_MASK(R_SERIAL0_READ, framing_err)) ) {  in handle_ser_rx_interrupt_no_dma()
2226 			if (data_read & IO_MASK(R_SERIAL0_READ, rxd)) {  in handle_ser_rx_interrupt_no_dma()
2254 				if (data_read & IO_MASK(R_SERIAL0_READ, par_err)) {  in handle_ser_rx_interrupt_no_dma()
2257 				} else if (data_read & IO_MASK(R_SERIAL0_READ, overrun)) {  in handle_ser_rx_interrupt_no_dma()
2260 				} else if (data_read & IO_MASK(R_SERIAL0_READ, framing_err)) {  in handle_ser_rx_interrupt_no_dma()
2269 	} else if (data_read & IO_MASK(R_SERIAL0_READ, data_avail)) {  in handle_ser_rx_interrupt_no_dma()
2290 	if (data_read & IO_MASK(R_SERIAL0_READ, data_avail)) {  in handle_ser_rx_interrupt_no_dma()
2312 	if (rstat & IO_MASK(R_SERIAL0_STATUS, xoff_detect) ) {  in handle_ser_rx_interrupt()
2552 		irq_mask1_rd &= (IO_MASK(R_IRQ_MASK1_RD, ser0_ready) |  in ser_interrupt()
2553 				 IO_MASK(R_IRQ_MASK1_RD, ser1_ready) |  in ser_interrupt()
2554 				 IO_MASK(R_IRQ_MASK1_RD, ser2_ready) |  in ser_interrupt()
2555 				 IO_MASK(R_IRQ_MASK1_RD, ser3_ready));  in ser_interrupt()
2583 		ready_mask = irq_mask1_rd & (IO_MASK(R_IRQ_MASK1_RD, ser0_ready) |  in ser_interrupt()
2584 					     IO_MASK(R_IRQ_MASK1_RD, ser1_ready) |  in ser_interrupt()
2585 					     IO_MASK(R_IRQ_MASK1_RD, ser2_ready) |  in ser_interrupt()
2586 					     IO_MASK(R_IRQ_MASK1_RD, ser3_ready));  in ser_interrupt()
2912 	info->rx_ctrl &= ~(IO_MASK(R_SERIAL0_REC_CTRL, rec_bitnr) |  in change_speed()
2913 			   IO_MASK(R_SERIAL0_REC_CTRL, rec_par_en) |  in change_speed()
2914 			   IO_MASK(R_SERIAL0_REC_CTRL, rec_par));  in change_speed()
2917 	info->tx_ctrl &= ~(IO_MASK(R_SERIAL0_TR_CTRL, tr_bitnr) |  in change_speed()
2918 			   IO_MASK(R_SERIAL0_TR_CTRL, tr_par_en) |  in change_speed()
2919 			   IO_MASK(R_SERIAL0_TR_CTRL, tr_par) |  in change_speed()
2920 			   IO_MASK(R_SERIAL0_TR_CTRL, stop_bits) |  in change_speed()
2921 			   IO_MASK(R_SERIAL0_TR_CTRL, auto_cts));  in change_speed()
4125 		if (rstat & IO_MASK(R_SERIAL0_STATUS, xoff_detect))  in seq_line_info()