266 static inline unsigned uts_reg(struct imx_port *sport)  in uts_reg()  argument
268 	return sport->devdata->uts_reg;  in uts_reg()
271 static inline int is_imx1_uart(struct imx_port *sport)  in is_imx1_uart()  argument
273 	return sport->devdata->devtype == IMX1_UART;  in is_imx1_uart()
276 static inline int is_imx21_uart(struct imx_port *sport)  in is_imx21_uart()  argument
278 	return sport->devdata->devtype == IMX21_UART;  in is_imx21_uart()
281 static inline int is_imx6q_uart(struct imx_port *sport)  in is_imx6q_uart()  argument
283 	return sport->devdata->devtype == IMX6Q_UART;  in is_imx6q_uart()
311 static void imx_mctrl_check(struct imx_port *sport)  in imx_mctrl_check()  argument
315 	status = sport->port.ops->get_mctrl(&sport->port);  in imx_mctrl_check()
316 	changed = status ^ sport->old_status;  in imx_mctrl_check()
321 	sport->old_status = status;  in imx_mctrl_check()
324 		sport->port.icount.rng++;  in imx_mctrl_check()
326 		sport->port.icount.dsr++;  in imx_mctrl_check()
328 		uart_handle_dcd_change(&sport->port, status & TIOCM_CAR);  in imx_mctrl_check()
330 		uart_handle_cts_change(&sport->port, status & TIOCM_CTS);  in imx_mctrl_check()
332 	wake_up_interruptible(&sport->port.state->port.delta_msr_wait);  in imx_mctrl_check()
341 	struct imx_port *sport = (struct imx_port *)data;  in imx_timeout()  local
344 	if (sport->port.state) {  in imx_timeout()
345 		spin_lock_irqsave(&sport->port.lock, flags);  in imx_timeout()
346 		imx_mctrl_check(sport);  in imx_timeout()
347 		spin_unlock_irqrestore(&sport->port.lock, flags);  in imx_timeout()
349 		mod_timer(&sport->timer, jiffies + MCTRL_TIMEOUT);  in imx_timeout()
358 	struct imx_port *sport = (struct imx_port *)port;  in imx_stop_tx()  local
365 	if (sport->dma_is_enabled && sport->dma_is_txing)  in imx_stop_tx()
392 	struct imx_port *sport = (struct imx_port *)port;  in imx_stop_rx()  local
395 	if (sport->dma_is_enabled && sport->dma_is_rxing) {  in imx_stop_rx()
396 		if (sport->port.suspended) {  in imx_stop_rx()
397 			dmaengine_terminate_all(sport->dma_chan_rx);  in imx_stop_rx()
398 			sport->dma_is_rxing = 0;  in imx_stop_rx()
404 	temp = readl(sport->port.membase + UCR2);  in imx_stop_rx()
405 	writel(temp & ~UCR2_RXEN, sport->port.membase + UCR2);  in imx_stop_rx()
408 	temp = readl(sport->port.membase + UCR1);  in imx_stop_rx()
409 	writel(temp & ~UCR1_RRDYEN, sport->port.membase + UCR1);  in imx_stop_rx()
417 	struct imx_port *sport = (struct imx_port *)port;  in imx_enable_ms()  local
419 	mod_timer(&sport->timer, jiffies);  in imx_enable_ms()
422 static void imx_dma_tx(struct imx_port *sport);
423 static inline void imx_transmit_buffer(struct imx_port *sport)  in imx_transmit_buffer()  argument
425 	struct circ_buf *xmit = &sport->port.state->xmit;  in imx_transmit_buffer()
428 	if (sport->port.x_char) {  in imx_transmit_buffer()
430 		writel(sport->port.x_char, sport->port.membase + URTX0);  in imx_transmit_buffer()
431 		sport->port.icount.tx++;  in imx_transmit_buffer()
432 		sport->port.x_char = 0;  in imx_transmit_buffer()
436 	if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) {  in imx_transmit_buffer()
437 		imx_stop_tx(&sport->port);  in imx_transmit_buffer()
441 	if (sport->dma_is_enabled) {  in imx_transmit_buffer()
446 		temp = readl(sport->port.membase + UCR1);  in imx_transmit_buffer()
448 		if (sport->dma_is_txing) {  in imx_transmit_buffer()
450 			writel(temp, sport->port.membase + UCR1);  in imx_transmit_buffer()
452 			writel(temp, sport->port.membase + UCR1);  in imx_transmit_buffer()
453 			imx_dma_tx(sport);  in imx_transmit_buffer()
458 	       !(readl(sport->port.membase + uts_reg(sport)) & UTS_TXFULL)) {  in imx_transmit_buffer()
461 		writel(xmit->buf[xmit->tail], sport->port.membase + URTX0);  in imx_transmit_buffer()
463 		sport->port.icount.tx++;  in imx_transmit_buffer()
467 		uart_write_wakeup(&sport->port);  in imx_transmit_buffer()
470 		imx_stop_tx(&sport->port);  in imx_transmit_buffer()
475 	struct imx_port *sport = data;  in dma_tx_callback()  local
476 	struct scatterlist *sgl = &sport->tx_sgl[0];  in dma_tx_callback()
477 	struct circ_buf *xmit = &sport->port.state->xmit;  in dma_tx_callback()
481 	spin_lock_irqsave(&sport->port.lock, flags);  in dma_tx_callback()
483 	dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);  in dma_tx_callback()
485 	temp = readl(sport->port.membase + UCR1);  in dma_tx_callback()
487 	writel(temp, sport->port.membase + UCR1);  in dma_tx_callback()
490 	xmit->tail = (xmit->tail + sport->tx_bytes) & (UART_XMIT_SIZE - 1);  in dma_tx_callback()
491 	sport->port.icount.tx += sport->tx_bytes;  in dma_tx_callback()
493 	dev_dbg(sport->port.dev, "we finish the TX DMA.\n");  in dma_tx_callback()
495 	sport->dma_is_txing = 0;  in dma_tx_callback()
497 	spin_unlock_irqrestore(&sport->port.lock, flags);  in dma_tx_callback()
500 		uart_write_wakeup(&sport->port);  in dma_tx_callback()
502 	if (waitqueue_active(&sport->dma_wait)) {  in dma_tx_callback()
503 		wake_up(&sport->dma_wait);  in dma_tx_callback()
504 		dev_dbg(sport->port.dev, "exit in %s.\n", __func__);  in dma_tx_callback()
508 	spin_lock_irqsave(&sport->port.lock, flags);  in dma_tx_callback()
509 	if (!uart_circ_empty(xmit) && !uart_tx_stopped(&sport->port))  in dma_tx_callback()
510 		imx_dma_tx(sport);  in dma_tx_callback()
511 	spin_unlock_irqrestore(&sport->port.lock, flags);  in dma_tx_callback()
514 static void imx_dma_tx(struct imx_port *sport)  in imx_dma_tx()  argument
516 	struct circ_buf *xmit = &sport->port.state->xmit;  in imx_dma_tx()
517 	struct scatterlist *sgl = sport->tx_sgl;  in imx_dma_tx()
519 	struct dma_chan	*chan = sport->dma_chan_tx;  in imx_dma_tx()
520 	struct device *dev = sport->port.dev;  in imx_dma_tx()
524 	if (sport->dma_is_txing)  in imx_dma_tx()
527 	sport->tx_bytes = uart_circ_chars_pending(xmit);  in imx_dma_tx()
530 		sport->dma_tx_nents = 1;  in imx_dma_tx()
531 		sg_init_one(sgl, xmit->buf + xmit->tail, sport->tx_bytes);  in imx_dma_tx()
533 		sport->dma_tx_nents = 2;  in imx_dma_tx()
540 	ret = dma_map_sg(dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);  in imx_dma_tx()
545 	desc = dmaengine_prep_slave_sg(chan, sgl, sport->dma_tx_nents,  in imx_dma_tx()
548 		dma_unmap_sg(dev, sgl, sport->dma_tx_nents,  in imx_dma_tx()
554 	desc->callback_param = sport;  in imx_dma_tx()
559 	temp = readl(sport->port.membase + UCR1);  in imx_dma_tx()
561 	writel(temp, sport->port.membase + UCR1);  in imx_dma_tx()
564 	sport->dma_is_txing = 1;  in imx_dma_tx()
575 	struct imx_port *sport = (struct imx_port *)port;  in imx_start_tx()  local
592 	if (!sport->dma_is_enabled) {  in imx_start_tx()
593 		temp = readl(sport->port.membase + UCR1);  in imx_start_tx()
594 		writel(temp | UCR1_TXMPTYEN, sport->port.membase + UCR1);  in imx_start_tx()
597 	if (sport->dma_is_enabled) {  in imx_start_tx()
598 		if (sport->port.x_char) {  in imx_start_tx()
601 			temp = readl(sport->port.membase + UCR1);  in imx_start_tx()
604 			writel(temp, sport->port.membase + UCR1);  in imx_start_tx()
610 			imx_dma_tx(sport);  in imx_start_tx()
617 	struct imx_port *sport = dev_id;  in imx_rtsint()  local
621 	spin_lock_irqsave(&sport->port.lock, flags);  in imx_rtsint()
623 	writel(USR1_RTSD, sport->port.membase + USR1);  in imx_rtsint()
624 	val = readl(sport->port.membase + USR1) & USR1_RTSS;  in imx_rtsint()
625 	uart_handle_cts_change(&sport->port, !!val);  in imx_rtsint()
626 	wake_up_interruptible(&sport->port.state->port.delta_msr_wait);  in imx_rtsint()
628 	spin_unlock_irqrestore(&sport->port.lock, flags);  in imx_rtsint()
634 	struct imx_port *sport = dev_id;  in imx_txint()  local
637 	spin_lock_irqsave(&sport->port.lock, flags);  in imx_txint()
638 	imx_transmit_buffer(sport);  in imx_txint()
639 	spin_unlock_irqrestore(&sport->port.lock, flags);  in imx_txint()
645 	struct imx_port *sport = dev_id;  in imx_rxint()  local
647 	struct tty_port *port = &sport->port.state->port;  in imx_rxint()
650 	spin_lock_irqsave(&sport->port.lock, flags);  in imx_rxint()
652 	while (readl(sport->port.membase + USR2) & USR2_RDR) {  in imx_rxint()
654 		sport->port.icount.rx++;  in imx_rxint()
656 		rx = readl(sport->port.membase + URXD0);  in imx_rxint()
658 		temp = readl(sport->port.membase + USR2);  in imx_rxint()
660 			writel(USR2_BRCD, sport->port.membase + USR2);  in imx_rxint()
661 			if (uart_handle_break(&sport->port))  in imx_rxint()
665 		if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx))  in imx_rxint()
670 				sport->port.icount.brk++;  in imx_rxint()
672 				sport->port.icount.parity++;  in imx_rxint()
674 				sport->port.icount.frame++;  in imx_rxint()
676 				sport->port.icount.overrun++;  in imx_rxint()
678 			if (rx & sport->port.ignore_status_mask) {  in imx_rxint()
684 			rx &= (sport->port.read_status_mask | 0xFF);  in imx_rxint()
696 			sport->port.sysrq = 0;  in imx_rxint()
700 		if (sport->port.ignore_status_mask & URXD_DUMMY_READ)  in imx_rxint()
707 	spin_unlock_irqrestore(&sport->port.lock, flags);  in imx_rxint()
712 static int start_rx_dma(struct imx_port *sport);
717 static void imx_dma_rxint(struct imx_port *sport)  in imx_dma_rxint()  argument
722 	spin_lock_irqsave(&sport->port.lock, flags);  in imx_dma_rxint()
724 	temp = readl(sport->port.membase + USR2);  in imx_dma_rxint()
725 	if ((temp & USR2_RDR) && !sport->dma_is_rxing) {  in imx_dma_rxint()
726 		sport->dma_is_rxing = 1;  in imx_dma_rxint()
729 		temp = readl(sport->port.membase + UCR1);  in imx_dma_rxint()
731 		writel(temp, sport->port.membase + UCR1);  in imx_dma_rxint()
734 		start_rx_dma(sport);  in imx_dma_rxint()
737 	spin_unlock_irqrestore(&sport->port.lock, flags);  in imx_dma_rxint()
742 	struct imx_port *sport = dev_id;  in imx_int()  local
746 	sts = readl(sport->port.membase + USR1);  in imx_int()
747 	sts2 = readl(sport->port.membase + USR2);  in imx_int()
750 		if (sport->dma_is_enabled)  in imx_int()
751 			imx_dma_rxint(sport);  in imx_int()
757 	     readl(sport->port.membase + UCR1) & UCR1_TXMPTYEN) ||  in imx_int()
759 	     readl(sport->port.membase + UCR4) & UCR4_TCEN))  in imx_int()
766 		writel(USR1_AWAKE, sport->port.membase + USR1);  in imx_int()
769 		dev_err(sport->port.dev, "Rx FIFO overrun\n");  in imx_int()
770 		sport->port.icount.overrun++;  in imx_int()
771 		writel(USR2_ORE, sport->port.membase + USR2);  in imx_int()
782 	struct imx_port *sport = (struct imx_port *)port;  in imx_tx_empty()  local
785 	ret = (readl(sport->port.membase + USR2) & USR2_TXDC) ?  TIOCSER_TEMT : 0;  in imx_tx_empty()
788 	if (sport->dma_is_enabled && sport->dma_is_txing)  in imx_tx_empty()
799 	struct imx_port *sport = (struct imx_port *)port;  in imx_get_mctrl()  local
802 	if (readl(sport->port.membase + USR1) & USR1_RTSS)  in imx_get_mctrl()
805 	if (readl(sport->port.membase + UCR2) & UCR2_CTS)  in imx_get_mctrl()
808 	if (readl(sport->port.membase + uts_reg(sport)) & UTS_LOOP)  in imx_get_mctrl()
816 	struct imx_port *sport = (struct imx_port *)port;  in imx_set_mctrl()  local
820 		temp = readl(sport->port.membase + UCR2);  in imx_set_mctrl()
824 		writel(temp, sport->port.membase + UCR2);  in imx_set_mctrl()
827 	temp = readl(sport->port.membase + uts_reg(sport)) & ~UTS_LOOP;  in imx_set_mctrl()
830 	writel(temp, sport->port.membase + uts_reg(sport));  in imx_set_mctrl()
838 	struct imx_port *sport = (struct imx_port *)port;  in imx_break_ctl()  local
841 	spin_lock_irqsave(&sport->port.lock, flags);  in imx_break_ctl()
843 	temp = readl(sport->port.membase + UCR1) & ~UCR1_SNDBRK;  in imx_break_ctl()
848 	writel(temp, sport->port.membase + UCR1);  in imx_break_ctl()
850 	spin_unlock_irqrestore(&sport->port.lock, flags);  in imx_break_ctl()
856 static int imx_setup_ufcr(struct imx_port *sport, unsigned int mode)  in imx_setup_ufcr()  argument
861 	val = readl(sport->port.membase + UFCR) & (UFCR_RFDIV | UFCR_DCEDTE);  in imx_setup_ufcr()
863 	writel(val, sport->port.membase + UFCR);  in imx_setup_ufcr()
868 static void imx_rx_dma_done(struct imx_port *sport)  in imx_rx_dma_done()  argument
873 	spin_lock_irqsave(&sport->port.lock, flags);  in imx_rx_dma_done()
876 	temp = readl(sport->port.membase + UCR1);  in imx_rx_dma_done()
878 	writel(temp, sport->port.membase + UCR1);  in imx_rx_dma_done()
880 	sport->dma_is_rxing = 0;  in imx_rx_dma_done()
883 	if (waitqueue_active(&sport->dma_wait))  in imx_rx_dma_done()
884 		wake_up(&sport->dma_wait);  in imx_rx_dma_done()
886 	spin_unlock_irqrestore(&sport->port.lock, flags);  in imx_rx_dma_done()
901 	struct imx_port *sport = data;  in dma_rx_callback()  local
902 	struct dma_chan	*chan = sport->dma_chan_rx;  in dma_rx_callback()
903 	struct scatterlist *sgl = &sport->rx_sgl;  in dma_rx_callback()
904 	struct tty_port *port = &sport->port.state->port;  in dma_rx_callback()
910 	dma_unmap_sg(sport->port.dev, sgl, 1, DMA_FROM_DEVICE);  in dma_rx_callback()
915 	if (readl(sport->port.membase + USR2) & USR2_IDLE) {  in dma_rx_callback()
919 		writel(USR2_IDLE, sport->port.membase + USR2);  in dma_rx_callback()
922 	dev_dbg(sport->port.dev, "We get %d bytes.\n", count);  in dma_rx_callback()
925 		if (!(sport->port.ignore_status_mask & URXD_DUMMY_READ))  in dma_rx_callback()
926 			tty_insert_flip_string(port, sport->rx_buf, count);  in dma_rx_callback()
929 		start_rx_dma(sport);  in dma_rx_callback()
930 	} else if (readl(sport->port.membase + USR2) & USR2_RDR) {  in dma_rx_callback()
937 		start_rx_dma(sport);  in dma_rx_callback()
943 		imx_rx_dma_done(sport);  in dma_rx_callback()
947 static int start_rx_dma(struct imx_port *sport)  in start_rx_dma()  argument
949 	struct scatterlist *sgl = &sport->rx_sgl;  in start_rx_dma()
950 	struct dma_chan	*chan = sport->dma_chan_rx;  in start_rx_dma()
951 	struct device *dev = sport->port.dev;  in start_rx_dma()
955 	sg_init_one(sgl, sport->rx_buf, RX_BUF_SIZE);  in start_rx_dma()
969 	desc->callback_param = sport;  in start_rx_dma()
977 static void imx_uart_dma_exit(struct imx_port *sport)  in imx_uart_dma_exit()  argument
979 	if (sport->dma_chan_rx) {  in imx_uart_dma_exit()
980 		dma_release_channel(sport->dma_chan_rx);  in imx_uart_dma_exit()
981 		sport->dma_chan_rx = NULL;  in imx_uart_dma_exit()
983 		kfree(sport->rx_buf);  in imx_uart_dma_exit()
984 		sport->rx_buf = NULL;  in imx_uart_dma_exit()
987 	if (sport->dma_chan_tx) {  in imx_uart_dma_exit()
988 		dma_release_channel(sport->dma_chan_tx);  in imx_uart_dma_exit()
989 		sport->dma_chan_tx = NULL;  in imx_uart_dma_exit()
992 	sport->dma_is_inited = 0;  in imx_uart_dma_exit()
995 static int imx_uart_dma_init(struct imx_port *sport)  in imx_uart_dma_init()  argument
998 	struct device *dev = sport->port.dev;  in imx_uart_dma_init()
1002 	sport->dma_chan_rx = dma_request_slave_channel(dev, "rx");  in imx_uart_dma_init()
1003 	if (!sport->dma_chan_rx) {  in imx_uart_dma_init()
1010 	slave_config.src_addr = sport->port.mapbase + URXD0;  in imx_uart_dma_init()
1013 	ret = dmaengine_slave_config(sport->dma_chan_rx, &slave_config);  in imx_uart_dma_init()
1019 	sport->rx_buf = kzalloc(PAGE_SIZE, GFP_KERNEL);  in imx_uart_dma_init()
1020 	if (!sport->rx_buf) {  in imx_uart_dma_init()
1026 	sport->dma_chan_tx = dma_request_slave_channel(dev, "tx");  in imx_uart_dma_init()
1027 	if (!sport->dma_chan_tx) {  in imx_uart_dma_init()
1034 	slave_config.dst_addr = sport->port.mapbase + URTX0;  in imx_uart_dma_init()
1037 	ret = dmaengine_slave_config(sport->dma_chan_tx, &slave_config);  in imx_uart_dma_init()
1043 	sport->dma_is_inited = 1;  in imx_uart_dma_init()
1047 	imx_uart_dma_exit(sport);  in imx_uart_dma_init()
1051 static void imx_enable_dma(struct imx_port *sport)  in imx_enable_dma()  argument
1055 	init_waitqueue_head(&sport->dma_wait);  in imx_enable_dma()
1058 	temp = readl(sport->port.membase + UCR1);  in imx_enable_dma()
1062 	writel(temp, sport->port.membase + UCR1);  in imx_enable_dma()
1065 	temp = readl(sport->port.membase + UCR4);  in imx_enable_dma()
1067 	writel(temp, sport->port.membase + UCR4);  in imx_enable_dma()
1069 	sport->dma_is_enabled = 1;  in imx_enable_dma()
1072 static void imx_disable_dma(struct imx_port *sport)  in imx_disable_dma()  argument
1077 	temp = readl(sport->port.membase + UCR1);  in imx_disable_dma()
1079 	writel(temp, sport->port.membase + UCR1);  in imx_disable_dma()
1082 	temp = readl(sport->port.membase + UCR2);  in imx_disable_dma()
1084 	writel(temp, sport->port.membase + UCR2);  in imx_disable_dma()
1087 	temp = readl(sport->port.membase + UCR4);  in imx_disable_dma()
1089 	writel(temp, sport->port.membase + UCR4);  in imx_disable_dma()
1091 	sport->dma_is_enabled = 0;  in imx_disable_dma()
1099 	struct imx_port *sport = (struct imx_port *)port;  in imx_startup()  local
1103 	retval = clk_prepare_enable(sport->clk_per);  in imx_startup()
1106 	retval = clk_prepare_enable(sport->clk_ipg);  in imx_startup()
1108 		clk_disable_unprepare(sport->clk_per);  in imx_startup()
1112 	imx_setup_ufcr(sport, 0);  in imx_startup()
1117 	temp = readl(sport->port.membase + UCR4);  in imx_startup()
1123 	writel(temp & ~UCR4_DREN, sport->port.membase + UCR4);  in imx_startup()
1128 	temp = readl(sport->port.membase + UCR2);  in imx_startup()
1130 	writel(temp, sport->port.membase + UCR2);  in imx_startup()
1132 	while (!(readl(sport->port.membase + UCR2) & UCR2_SRST) && (--i > 0))  in imx_startup()
1135 	spin_lock_irqsave(&sport->port.lock, flags);  in imx_startup()
1140 	writel(USR1_RTSD, sport->port.membase + USR1);  in imx_startup()
1141 	writel(USR2_ORE, sport->port.membase + USR2);  in imx_startup()
1143 	temp = readl(sport->port.membase + UCR1);  in imx_startup()
1146 	writel(temp, sport->port.membase + UCR1);  in imx_startup()
1148 	temp = readl(sport->port.membase + UCR4);  in imx_startup()
1150 	writel(temp, sport->port.membase + UCR4);  in imx_startup()
1152 	temp = readl(sport->port.membase + UCR2);  in imx_startup()
1154 	if (!sport->have_rtscts)  in imx_startup()
1156 	writel(temp, sport->port.membase + UCR2);  in imx_startup()
1158 	if (!is_imx1_uart(sport)) {  in imx_startup()
1159 		temp = readl(sport->port.membase + UCR3);  in imx_startup()
1161 		writel(temp, sport->port.membase + UCR3);  in imx_startup()
1167 	imx_enable_ms(&sport->port);  in imx_startup()
1168 	spin_unlock_irqrestore(&sport->port.lock, flags);  in imx_startup()
1175 	struct imx_port *sport = (struct imx_port *)port;  in imx_shutdown()  local
1179 	if (sport->dma_is_enabled) {  in imx_shutdown()
1183 		ret = wait_event_interruptible(sport->dma_wait,  in imx_shutdown()
1184 			!sport->dma_is_rxing && !sport->dma_is_txing);  in imx_shutdown()
1186 			sport->dma_is_rxing = 0;  in imx_shutdown()
1187 			sport->dma_is_txing = 0;  in imx_shutdown()
1188 			dmaengine_terminate_all(sport->dma_chan_tx);  in imx_shutdown()
1189 			dmaengine_terminate_all(sport->dma_chan_rx);  in imx_shutdown()
1191 		spin_lock_irqsave(&sport->port.lock, flags);  in imx_shutdown()
1194 		imx_disable_dma(sport);  in imx_shutdown()
1195 		spin_unlock_irqrestore(&sport->port.lock, flags);  in imx_shutdown()
1196 		imx_uart_dma_exit(sport);  in imx_shutdown()
1199 	spin_lock_irqsave(&sport->port.lock, flags);  in imx_shutdown()
1200 	temp = readl(sport->port.membase + UCR2);  in imx_shutdown()
1202 	writel(temp, sport->port.membase + UCR2);  in imx_shutdown()
1203 	spin_unlock_irqrestore(&sport->port.lock, flags);  in imx_shutdown()
1208 	del_timer_sync(&sport->timer);  in imx_shutdown()
1214 	spin_lock_irqsave(&sport->port.lock, flags);  in imx_shutdown()
1215 	temp = readl(sport->port.membase + UCR1);  in imx_shutdown()
1218 	writel(temp, sport->port.membase + UCR1);  in imx_shutdown()
1219 	spin_unlock_irqrestore(&sport->port.lock, flags);  in imx_shutdown()
1221 	clk_disable_unprepare(sport->clk_per);  in imx_shutdown()
1222 	clk_disable_unprepare(sport->clk_ipg);  in imx_shutdown()
1227 	struct imx_port *sport = (struct imx_port *)port;  in imx_flush_buffer()  local
1228 	struct scatterlist *sgl = &sport->tx_sgl[0];  in imx_flush_buffer()
1232 	if (!sport->dma_chan_tx)  in imx_flush_buffer()
1235 	sport->tx_bytes = 0;  in imx_flush_buffer()
1236 	dmaengine_terminate_all(sport->dma_chan_tx);  in imx_flush_buffer()
1237 	if (sport->dma_is_txing) {  in imx_flush_buffer()
1238 		dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents,  in imx_flush_buffer()
1240 		temp = readl(sport->port.membase + UCR1);  in imx_flush_buffer()
1242 		writel(temp, sport->port.membase + UCR1);  in imx_flush_buffer()
1243 		sport->dma_is_txing = false;  in imx_flush_buffer()
1253 	ubir = readl(sport->port.membase + UBIR);  in imx_flush_buffer()
1254 	ubmr = readl(sport->port.membase + UBMR);  in imx_flush_buffer()
1255 	uts = readl(sport->port.membase + IMX21_UTS);  in imx_flush_buffer()
1257 	temp = readl(sport->port.membase + UCR2);  in imx_flush_buffer()
1259 	writel(temp, sport->port.membase + UCR2);  in imx_flush_buffer()
1261 	while (!(readl(sport->port.membase + UCR2) & UCR2_SRST) && (--i > 0))  in imx_flush_buffer()
1265 	writel(ubir, sport->port.membase + UBIR);  in imx_flush_buffer()
1266 	writel(ubmr, sport->port.membase + UBMR);  in imx_flush_buffer()
1267 	writel(uts, sport->port.membase + IMX21_UTS);  in imx_flush_buffer()
1274 	struct imx_port *sport = (struct imx_port *)port;  in imx_set_termios()  local
1298 		if (sport->have_rtscts) {  in imx_set_termios()
1315 			if (is_imx6q_uart(sport) && !uart_console(port)  in imx_set_termios()
1316 				&& !sport->dma_is_inited)  in imx_set_termios()
1317 				imx_uart_dma_init(sport);  in imx_set_termios()
1334 	del_timer_sync(&sport->timer);  in imx_set_termios()
1342 	spin_lock_irqsave(&sport->port.lock, flags);  in imx_set_termios()
1344 	sport->port.read_status_mask = 0;  in imx_set_termios()
1346 		sport->port.read_status_mask |= (URXD_FRMERR | URXD_PRERR);  in imx_set_termios()
1348 		sport->port.read_status_mask |= URXD_BRK;  in imx_set_termios()
1353 	sport->port.ignore_status_mask = 0;  in imx_set_termios()
1355 		sport->port.ignore_status_mask |= URXD_PRERR | URXD_FRMERR;  in imx_set_termios()
1357 		sport->port.ignore_status_mask |= URXD_BRK;  in imx_set_termios()
1363 			sport->port.ignore_status_mask |= URXD_OVRRUN;  in imx_set_termios()
1367 		sport->port.ignore_status_mask |= URXD_DUMMY_READ;  in imx_set_termios()
1377 	old_ucr1 = readl(sport->port.membase + UCR1);  in imx_set_termios()
1379 			sport->port.membase + UCR1);  in imx_set_termios()
1381 	while (!(readl(sport->port.membase + USR2) & USR2_TXDC))  in imx_set_termios()
1385 	old_txrxen = readl(sport->port.membase + UCR2);  in imx_set_termios()
1387 			sport->port.membase + UCR2);  in imx_set_termios()
1391 	div = sport->port.uartclk / (baud * 16);  in imx_set_termios()
1393 		baud = sport->port.uartclk / (quot * 16);  in imx_set_termios()
1395 	div = sport->port.uartclk / (baud * 16);  in imx_set_termios()
1401 	rational_best_approximation(16 * div * baud, sport->port.uartclk,  in imx_set_termios()
1404 	tdiv64 = sport->port.uartclk;  in imx_set_termios()
1413 	ufcr = readl(sport->port.membase + UFCR);  in imx_set_termios()
1415 	if (sport->dte_mode)  in imx_set_termios()
1417 	writel(ufcr, sport->port.membase + UFCR);  in imx_set_termios()
1419 	writel(num, sport->port.membase + UBIR);  in imx_set_termios()
1420 	writel(denom, sport->port.membase + UBMR);  in imx_set_termios()
1422 	if (!is_imx1_uart(sport))  in imx_set_termios()
1423 		writel(sport->port.uartclk / div / 1000,  in imx_set_termios()
1424 				sport->port.membase + IMX21_ONEMS);  in imx_set_termios()
1426 	writel(old_ucr1, sport->port.membase + UCR1);  in imx_set_termios()
1429 	writel(ucr2 | old_txrxen, sport->port.membase + UCR2);  in imx_set_termios()
1431 	if (UART_ENABLE_MS(&sport->port, termios->c_cflag))  in imx_set_termios()
1432 		imx_enable_ms(&sport->port);  in imx_set_termios()
1434 	if (sport->dma_is_inited && !sport->dma_is_enabled)  in imx_set_termios()
1435 		imx_enable_dma(sport);  in imx_set_termios()
1436 	spin_unlock_irqrestore(&sport->port.lock, flags);  in imx_set_termios()
1441 	struct imx_port *sport = (struct imx_port *)port;  in imx_type()  local
1443 	return sport->port.type == PORT_IMX ? "IMX" : NULL;  in imx_type()
1451 	struct imx_port *sport = (struct imx_port *)port;  in imx_config_port()  local
1454 		sport->port.type = PORT_IMX;  in imx_config_port()
1465 	struct imx_port *sport = (struct imx_port *)port;  in imx_verify_port()  local
1470 	if (sport->port.irq != ser->irq)  in imx_verify_port()
1474 	if (sport->port.uartclk / 16 != ser->baud_base)  in imx_verify_port()
1476 	if (sport->port.mapbase != (unsigned long)ser->iomem_base)  in imx_verify_port()
1478 	if (sport->port.iobase != ser->port)  in imx_verify_port()
1489 	struct imx_port *sport = (struct imx_port *)port;  in imx_poll_init()  local
1494 	retval = clk_prepare_enable(sport->clk_ipg);  in imx_poll_init()
1497 	retval = clk_prepare_enable(sport->clk_per);  in imx_poll_init()
1499 		clk_disable_unprepare(sport->clk_ipg);  in imx_poll_init()
1501 	imx_setup_ufcr(sport, 0);  in imx_poll_init()
1503 	spin_lock_irqsave(&sport->port.lock, flags);  in imx_poll_init()
1505 	temp = readl(sport->port.membase + UCR1);  in imx_poll_init()
1506 	if (is_imx1_uart(sport))  in imx_poll_init()
1510 	writel(temp, sport->port.membase + UCR1);  in imx_poll_init()
1512 	temp = readl(sport->port.membase + UCR2);  in imx_poll_init()
1514 	writel(temp, sport->port.membase + UCR2);  in imx_poll_init()
1516 	spin_unlock_irqrestore(&sport->port.lock, flags);  in imx_poll_init()
1551 	struct imx_port *sport = (struct imx_port *)port;  in imx_rs485_config()  local
1559 	if (!sport->have_rtscts)  in imx_rs485_config()
1566 		temp = readl(sport->port.membase + UCR2);  in imx_rs485_config()
1572 		writel(temp, sport->port.membase + UCR2);  in imx_rs485_config()
1608 	struct imx_port *sport = (struct imx_port *)port;  in imx_console_putchar()  local
1610 	while (readl(sport->port.membase + uts_reg(sport)) & UTS_TXFULL)  in imx_console_putchar()
1613 	writel(ch, sport->port.membase + URTX0);  in imx_console_putchar()
1622 	struct imx_port *sport = imx_ports[co->index];  in imx_console_write()  local
1629 	retval = clk_enable(sport->clk_per);  in imx_console_write()
1632 	retval = clk_enable(sport->clk_ipg);  in imx_console_write()
1634 		clk_disable(sport->clk_per);  in imx_console_write()
1638 	if (sport->port.sysrq)  in imx_console_write()
1641 		locked = spin_trylock_irqsave(&sport->port.lock, flags);  in imx_console_write()
1643 		spin_lock_irqsave(&sport->port.lock, flags);  in imx_console_write()
1648 	imx_port_ucrs_save(&sport->port, &old_ucr);  in imx_console_write()
1651 	if (is_imx1_uart(sport))  in imx_console_write()
1656 	writel(ucr1, sport->port.membase + UCR1);  in imx_console_write()
1658 	writel(old_ucr.ucr2 | UCR2_TXEN, sport->port.membase + UCR2);  in imx_console_write()
1660 	uart_console_write(&sport->port, s, count, imx_console_putchar);  in imx_console_write()
1666 	while (!(readl(sport->port.membase + USR2) & USR2_TXDC));  in imx_console_write()
1668 	imx_port_ucrs_restore(&sport->port, &old_ucr);  in imx_console_write()
1671 		spin_unlock_irqrestore(&sport->port.lock, flags);  in imx_console_write()
1673 	clk_disable(sport->clk_ipg);  in imx_console_write()
1674 	clk_disable(sport->clk_per);  in imx_console_write()
1682 imx_console_get_options(struct imx_port *sport, int *baud,  in imx_console_get_options()  argument
1686 	if (readl(sport->port.membase + UCR1) & UCR1_UARTEN) {  in imx_console_get_options()
1692 		ucr2 = readl(sport->port.membase + UCR2);  in imx_console_get_options()
1707 		ubir = readl(sport->port.membase + UBIR) & 0xffff;  in imx_console_get_options()
1708 		ubmr = readl(sport->port.membase + UBMR) & 0xffff;  in imx_console_get_options()
1710 		ucfr_rfdiv = (readl(sport->port.membase + UFCR) & UFCR_RFDIV) >> 7;  in imx_console_get_options()
1716 		uartclk = clk_get_rate(sport->clk_per);  in imx_console_get_options()
1743 	struct imx_port *sport;  in imx_console_setup()  local
1757 	sport = imx_ports[co->index];  in imx_console_setup()
1758 	if (sport == NULL)  in imx_console_setup()
1762 	retval = clk_prepare_enable(sport->clk_ipg);  in imx_console_setup()
1769 		imx_console_get_options(sport, &baud, &parity, &bits);  in imx_console_setup()
1771 	imx_setup_ufcr(sport, 0);  in imx_console_setup()
1773 	retval = uart_set_options(&sport->port, co, baud, parity, bits, flow);  in imx_console_setup()
1775 	clk_disable(sport->clk_ipg);  in imx_console_setup()
1777 		clk_unprepare(sport->clk_ipg);  in imx_console_setup()
1781 	retval = clk_prepare(sport->clk_per);  in imx_console_setup()
1783 		clk_disable_unprepare(sport->clk_ipg);  in imx_console_setup()
1817 	struct imx_port *sport = platform_get_drvdata(dev);  in serial_imx_suspend()  local
1821 	val = readl(sport->port.membase + UCR3);  in serial_imx_suspend()
1823 	writel(val, sport->port.membase + UCR3);  in serial_imx_suspend()
1825 	uart_suspend_port(&imx_reg, &sport->port);  in serial_imx_suspend()
1832 	struct imx_port *sport = platform_get_drvdata(dev);  in serial_imx_resume()  local
1836 	val = readl(sport->port.membase + UCR3);  in serial_imx_resume()
1838 	writel(val, sport->port.membase + UCR3);  in serial_imx_resume()
1840 	uart_resume_port(&imx_reg, &sport->port);  in serial_imx_resume()
1850 static int serial_imx_probe_dt(struct imx_port *sport,  in serial_imx_probe_dt()  argument
1867 	sport->port.line = ret;  in serial_imx_probe_dt()
1870 		sport->have_rtscts = 1;  in serial_imx_probe_dt()
1873 		sport->dte_mode = 1;  in serial_imx_probe_dt()
1875 	sport->devdata = of_id->data;  in serial_imx_probe_dt()
1880 static inline int serial_imx_probe_dt(struct imx_port *sport,  in serial_imx_probe_dt()  argument
1887 static void serial_imx_probe_pdata(struct imx_port *sport,  in serial_imx_probe_pdata()  argument
1892 	sport->port.line = pdev->id;  in serial_imx_probe_pdata()
1893 	sport->devdata = (struct imx_uart_data	*) pdev->id_entry->driver_data;  in serial_imx_probe_pdata()
1899 		sport->have_rtscts = 1;  in serial_imx_probe_pdata()
1904 	struct imx_port *sport;  in serial_imx_probe()  local
1910 	sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL);  in serial_imx_probe()
1911 	if (!sport)  in serial_imx_probe()
1914 	ret = serial_imx_probe_dt(sport, pdev);  in serial_imx_probe()
1916 		serial_imx_probe_pdata(sport, pdev);  in serial_imx_probe()
1929 	sport->port.dev = &pdev->dev;  in serial_imx_probe()
1930 	sport->port.mapbase = res->start;  in serial_imx_probe()
1931 	sport->port.membase = base;  in serial_imx_probe()
1932 	sport->port.type = PORT_IMX,  in serial_imx_probe()
1933 	sport->port.iotype = UPIO_MEM;  in serial_imx_probe()
1934 	sport->port.irq = rxirq;  in serial_imx_probe()
1935 	sport->port.fifosize = 32;  in serial_imx_probe()
1936 	sport->port.ops = &imx_pops;  in serial_imx_probe()
1937 	sport->port.rs485_config = imx_rs485_config;  in serial_imx_probe()
1938 	sport->port.rs485.flags =  in serial_imx_probe()
1940 	sport->port.flags = UPF_BOOT_AUTOCONF;  in serial_imx_probe()
1941 	init_timer(&sport->timer);  in serial_imx_probe()
1942 	sport->timer.function = imx_timeout;  in serial_imx_probe()
1943 	sport->timer.data     = (unsigned long)sport;  in serial_imx_probe()
1945 	sport->clk_ipg = devm_clk_get(&pdev->dev, "ipg");  in serial_imx_probe()
1946 	if (IS_ERR(sport->clk_ipg)) {  in serial_imx_probe()
1947 		ret = PTR_ERR(sport->clk_ipg);  in serial_imx_probe()
1952 	sport->clk_per = devm_clk_get(&pdev->dev, "per");  in serial_imx_probe()
1953 	if (IS_ERR(sport->clk_per)) {  in serial_imx_probe()
1954 		ret = PTR_ERR(sport->clk_per);  in serial_imx_probe()
1959 	sport->port.uartclk = clk_get_rate(sport->clk_per);  in serial_imx_probe()
1967 				       dev_name(&pdev->dev), sport);  in serial_imx_probe()
1972 				       dev_name(&pdev->dev), sport);  in serial_imx_probe()
1977 				       dev_name(&pdev->dev), sport);  in serial_imx_probe()
1982 	imx_ports[sport->port.line] = sport;  in serial_imx_probe()
1984 	platform_set_drvdata(pdev, sport);  in serial_imx_probe()
1986 	return uart_add_one_port(&imx_reg, &sport->port);  in serial_imx_probe()
1991 	struct imx_port *sport = platform_get_drvdata(pdev);  in serial_imx_remove()  local
1993 	return uart_remove_one_port(&imx_reg, &sport->port);  in serial_imx_remove()