67 	msm_write(port, UART_CR_CMD_RESET_TX_READY, UART_CR);  in wait_for_xmitr()
112 		msm_write(port, UART_CR_CMD_RESET_ERR, UART_CR);  in handle_rx_dm()
169 		msm_write(port, UART_CR_CMD_RESET_STALE_INT, UART_CR);  in handle_rx_dm()
171 	msm_write(port, UART_CR_CMD_STALE_EVENT_ENABLE, UART_CR);  in handle_rx_dm()
186 		msm_write(port, UART_CR_CMD_RESET_ERR, UART_CR);  in handle_rx()
295 	msm_write(port, UART_CR_CMD_RESET_CTS, UART_CR);  in handle_delta_cts()
312 		msm_write(port, UART_CR_CMD_RESET_RXBREAK_START, UART_CR);  in msm_irq()
347 	msm_write(port, UART_CR_CMD_RESET_RX, UART_CR);  in msm_reset()
348 	msm_write(port, UART_CR_CMD_RESET_TX, UART_CR);  in msm_reset()
349 	msm_write(port, UART_CR_CMD_RESET_ERR, UART_CR);  in msm_reset()
350 	msm_write(port, UART_CR_CMD_RESET_BREAK_INT, UART_CR);  in msm_reset()
351 	msm_write(port, UART_CR_CMD_RESET_CTS, UART_CR);  in msm_reset()
352 	msm_write(port, UART_CR_CMD_SET_RFR, UART_CR);  in msm_reset()
368 		msm_write(port, UART_CR_CMD_RESET_RFR, UART_CR);  in msm_set_mctrl()
378 		msm_write(port, UART_CR_CMD_START_BREAK, UART_CR);  in msm_break_ctl()
380 		msm_write(port, UART_CR_CMD_STOP_BREAK, UART_CR);  in msm_break_ctl()
446 	msm_write(port, UART_CR_CMD_PROTECTION_EN, UART_CR);  in msm_set_baud_rate()
450 	msm_write(port, UART_CR_TX_ENABLE | UART_CR_RX_ENABLE, UART_CR);  in msm_set_baud_rate()
459 		msm_write(port, UART_CR_CMD_RESET_STALE_INT, UART_CR);  in msm_set_baud_rate()
461 		msm_write(port, UART_CR_CMD_STALE_EVENT_ENABLE, UART_CR);  in msm_set_baud_rate()
716 			msm_write(port, UART_CR_CMD_FORCE_STALE, UART_CR);  in msm_poll_get_char_dm()
720 			msm_write(port, UART_CR_CMD_RESET_STALE_INT, UART_CR);  in msm_poll_get_char_dm()
723 				  UART_CR);  in msm_poll_get_char_dm()