Lines Matching refs:uap
104 #define pmz_debug(fmt, arg...) pr_debug("ttyPZ%d: " fmt, uap->port.line, ## arg)
105 #define pmz_error(fmt, arg...) pr_err("ttyPZ%d: " fmt, uap->port.line, ## arg)
106 #define pmz_info(fmt, arg...) pr_info("ttyPZ%d: " fmt, uap->port.line, ## arg)
129 static void pmz_load_zsregs(struct uart_pmac_port *uap, u8 *regs) in pmz_load_zsregs() argument
135 unsigned char stat = read_zsreg(uap, R1); in pmz_load_zsregs()
141 ZS_CLEARERR(uap); in pmz_load_zsregs()
142 zssync(uap); in pmz_load_zsregs()
143 ZS_CLEARFIFO(uap); in pmz_load_zsregs()
144 zssync(uap); in pmz_load_zsregs()
145 ZS_CLEARERR(uap); in pmz_load_zsregs()
148 write_zsreg(uap, R1, in pmz_load_zsregs()
152 write_zsreg(uap, R4, regs[R4]); in pmz_load_zsregs()
155 write_zsreg(uap, R10, regs[R10]); in pmz_load_zsregs()
158 write_zsreg(uap, R3, regs[R3] & ~RxENABLE); in pmz_load_zsregs()
159 write_zsreg(uap, R5, regs[R5] & ~TxENABLE); in pmz_load_zsregs()
162 write_zsreg(uap, R15, regs[R15] | EN85C30); in pmz_load_zsregs()
163 write_zsreg(uap, R7, regs[R7P]); in pmz_load_zsregs()
166 write_zsreg(uap, R15, regs[R15] & ~EN85C30); in pmz_load_zsregs()
169 write_zsreg(uap, R6, regs[R6]); in pmz_load_zsregs()
170 write_zsreg(uap, R7, regs[R7]); in pmz_load_zsregs()
173 write_zsreg(uap, R14, regs[R14] & ~BRENAB); in pmz_load_zsregs()
176 write_zsreg(uap, R11, regs[R11]); in pmz_load_zsregs()
179 write_zsreg(uap, R12, regs[R12]); in pmz_load_zsregs()
180 write_zsreg(uap, R13, regs[R13]); in pmz_load_zsregs()
183 write_zsreg(uap, R14, regs[R14]); in pmz_load_zsregs()
186 write_zsreg(uap, R0, RES_EXT_INT); in pmz_load_zsregs()
187 write_zsreg(uap, R0, RES_EXT_INT); in pmz_load_zsregs()
190 write_zsreg(uap, R3, regs[R3]); in pmz_load_zsregs()
191 write_zsreg(uap, R5, regs[R5]); in pmz_load_zsregs()
194 write_zsreg(uap, R1, regs[R1]); in pmz_load_zsregs()
197 write_zsreg(uap, R9, regs[R9]); in pmz_load_zsregs()
208 static void pmz_maybe_update_regs(struct uart_pmac_port *uap) in pmz_maybe_update_regs() argument
210 if (!ZS_REGS_HELD(uap)) { in pmz_maybe_update_regs()
211 if (ZS_TX_ACTIVE(uap)) { in pmz_maybe_update_regs()
212 uap->flags |= PMACZILOG_FLAG_REGS_HELD; in pmz_maybe_update_regs()
215 pmz_load_zsregs(uap, uap->curregs); in pmz_maybe_update_regs()
220 static void pmz_interrupt_control(struct uart_pmac_port *uap, int enable) in pmz_interrupt_control() argument
223 uap->curregs[1] |= INT_ALL_Rx | TxINT_ENAB; in pmz_interrupt_control()
224 if (!ZS_IS_EXTCLK(uap)) in pmz_interrupt_control()
225 uap->curregs[1] |= EXT_INT_ENAB; in pmz_interrupt_control()
227 uap->curregs[1] &= ~(EXT_INT_ENAB | TxINT_ENAB | RxINT_MASK); in pmz_interrupt_control()
229 write_zsreg(uap, R1, uap->curregs[1]); in pmz_interrupt_control()
232 static bool pmz_receive_chars(struct uart_pmac_port *uap) in pmz_receive_chars() argument
239 if (uap->port.state == NULL) { in pmz_receive_chars()
241 (void)read_zsdata(uap); in pmz_receive_chars()
244 port = &uap->port.state->port; in pmz_receive_chars()
250 r1 = read_zsreg(uap, R1); in pmz_receive_chars()
251 ch = read_zsdata(uap); in pmz_receive_chars()
254 write_zsreg(uap, R0, ERR_RES); in pmz_receive_chars()
255 zssync(uap); in pmz_receive_chars()
258 ch &= uap->parity_mask; in pmz_receive_chars()
259 if (ch == 0 && uap->flags & PMACZILOG_FLAG_BREAK) { in pmz_receive_chars()
260 uap->flags &= ~PMACZILOG_FLAG_BREAK; in pmz_receive_chars()
267 uap->port.sysrq = jiffies + HZ*5; in pmz_receive_chars()
271 if (uap->port.sysrq) { in pmz_receive_chars()
273 spin_unlock(&uap->port.lock); in pmz_receive_chars()
274 swallow = uart_handle_sysrq_char(&uap->port, ch); in pmz_receive_chars()
275 spin_lock(&uap->port.lock); in pmz_receive_chars()
286 uap->port.icount.rx++; in pmz_receive_chars()
293 uap->port.icount.brk++; in pmz_receive_chars()
294 if (uart_handle_break(&uap->port)) in pmz_receive_chars()
298 uap->port.icount.parity++; in pmz_receive_chars()
300 uap->port.icount.frame++; in pmz_receive_chars()
302 uap->port.icount.overrun++; in pmz_receive_chars()
303 r1 &= uap->port.read_status_mask; in pmz_receive_chars()
312 if (uap->port.ignore_status_mask == 0xff || in pmz_receive_chars()
313 (r1 & uap->port.ignore_status_mask) == 0) { in pmz_receive_chars()
328 ch = read_zsreg(uap, R0); in pmz_receive_chars()
335 pmz_interrupt_control(uap, 0); in pmz_receive_chars()
340 static void pmz_status_handle(struct uart_pmac_port *uap) in pmz_status_handle() argument
344 status = read_zsreg(uap, R0); in pmz_status_handle()
345 write_zsreg(uap, R0, RES_EXT_INT); in pmz_status_handle()
346 zssync(uap); in pmz_status_handle()
348 if (ZS_IS_OPEN(uap) && ZS_WANTS_MODEM_STATUS(uap)) { in pmz_status_handle()
350 uap->port.icount.dsr++; in pmz_status_handle()
357 if ((status ^ uap->prev_status) & DCD) in pmz_status_handle()
358 uart_handle_dcd_change(&uap->port, in pmz_status_handle()
360 if ((status ^ uap->prev_status) & CTS) in pmz_status_handle()
361 uart_handle_cts_change(&uap->port, in pmz_status_handle()
364 wake_up_interruptible(&uap->port.state->port.delta_msr_wait); in pmz_status_handle()
368 uap->flags |= PMACZILOG_FLAG_BREAK; in pmz_status_handle()
370 uap->prev_status = status; in pmz_status_handle()
373 static void pmz_transmit_chars(struct uart_pmac_port *uap) in pmz_transmit_chars() argument
377 if (ZS_IS_CONS(uap)) { in pmz_transmit_chars()
378 unsigned char status = read_zsreg(uap, R0); in pmz_transmit_chars()
392 uap->flags &= ~PMACZILOG_FLAG_TX_ACTIVE; in pmz_transmit_chars()
394 if (ZS_REGS_HELD(uap)) { in pmz_transmit_chars()
395 pmz_load_zsregs(uap, uap->curregs); in pmz_transmit_chars()
396 uap->flags &= ~PMACZILOG_FLAG_REGS_HELD; in pmz_transmit_chars()
399 if (ZS_TX_STOPPED(uap)) { in pmz_transmit_chars()
400 uap->flags &= ~PMACZILOG_FLAG_TX_STOPPED; in pmz_transmit_chars()
412 if (!ZS_IS_OPEN(uap)) in pmz_transmit_chars()
415 if (uap->port.x_char) { in pmz_transmit_chars()
416 uap->flags |= PMACZILOG_FLAG_TX_ACTIVE; in pmz_transmit_chars()
417 write_zsdata(uap, uap->port.x_char); in pmz_transmit_chars()
418 zssync(uap); in pmz_transmit_chars()
419 uap->port.icount.tx++; in pmz_transmit_chars()
420 uap->port.x_char = 0; in pmz_transmit_chars()
424 if (uap->port.state == NULL) in pmz_transmit_chars()
426 xmit = &uap->port.state->xmit; in pmz_transmit_chars()
428 uart_write_wakeup(&uap->port); in pmz_transmit_chars()
431 if (uart_tx_stopped(&uap->port)) in pmz_transmit_chars()
434 uap->flags |= PMACZILOG_FLAG_TX_ACTIVE; in pmz_transmit_chars()
435 write_zsdata(uap, xmit->buf[xmit->tail]); in pmz_transmit_chars()
436 zssync(uap); in pmz_transmit_chars()
439 uap->port.icount.tx++; in pmz_transmit_chars()
442 uart_write_wakeup(&uap->port); in pmz_transmit_chars()
447 write_zsreg(uap, R0, RES_Tx_P); in pmz_transmit_chars()
448 zssync(uap); in pmz_transmit_chars()
454 struct uart_pmac_port *uap = dev_id; in pmz_interrupt() local
461 uap_a = pmz_get_port_A(uap); in pmz_interrupt()
490 tty_flip_buffer_push(&uap->port.state->port); in pmz_interrupt()
515 tty_flip_buffer_push(&uap->port.state->port); in pmz_interrupt()
524 static inline u8 pmz_peek_status(struct uart_pmac_port *uap) in pmz_peek_status() argument
529 spin_lock_irqsave(&uap->port.lock, flags); in pmz_peek_status()
530 status = read_zsreg(uap, R0); in pmz_peek_status()
531 spin_unlock_irqrestore(&uap->port.lock, flags); in pmz_peek_status()
558 struct uart_pmac_port *uap = to_pmz(port); in pmz_set_mctrl() local
562 if (ZS_IS_IRDA(uap)) in pmz_set_mctrl()
565 if (!(ZS_IS_OPEN(uap) || ZS_IS_CONS(uap))) in pmz_set_mctrl()
570 if (ZS_IS_INTMODEM(uap)) { in pmz_set_mctrl()
582 uap->curregs[R5] |= set_bits; in pmz_set_mctrl()
583 uap->curregs[R5] &= ~clear_bits; in pmz_set_mctrl()
585 write_zsreg(uap, R5, uap->curregs[R5]); in pmz_set_mctrl()
587 set_bits, clear_bits, uap->curregs[R5]); in pmz_set_mctrl()
588 zssync(uap); in pmz_set_mctrl()
598 struct uart_pmac_port *uap = to_pmz(port); in pmz_get_mctrl() local
602 status = read_zsreg(uap, R0); in pmz_get_mctrl()
631 struct uart_pmac_port *uap = to_pmz(port); in pmz_start_tx() local
636 uap->flags |= PMACZILOG_FLAG_TX_ACTIVE; in pmz_start_tx()
637 uap->flags &= ~PMACZILOG_FLAG_TX_STOPPED; in pmz_start_tx()
639 status = read_zsreg(uap, R0); in pmz_start_tx()
649 write_zsdata(uap, port->x_char); in pmz_start_tx()
650 zssync(uap); in pmz_start_tx()
658 write_zsdata(uap, xmit->buf[xmit->tail]); in pmz_start_tx()
659 zssync(uap); in pmz_start_tx()
664 uart_write_wakeup(&uap->port); in pmz_start_tx()
678 struct uart_pmac_port *uap = to_pmz(port); in pmz_stop_rx() local
683 uap->curregs[R1] &= ~RxINT_MASK; in pmz_stop_rx()
684 pmz_maybe_update_regs(uap); in pmz_stop_rx()
695 struct uart_pmac_port *uap = to_pmz(port); in pmz_enable_ms() local
698 if (ZS_IS_IRDA(uap)) in pmz_enable_ms()
700 new_reg = uap->curregs[R15] | (DCDIE | SYNCIE | CTSIE); in pmz_enable_ms()
701 if (new_reg != uap->curregs[R15]) { in pmz_enable_ms()
702 uap->curregs[R15] = new_reg; in pmz_enable_ms()
705 write_zsreg(uap, R15, uap->curregs[R15]); in pmz_enable_ms()
715 struct uart_pmac_port *uap = to_pmz(port); in pmz_break_ctl() local
728 new_reg = (uap->curregs[R5] | set_bits) & ~clear_bits; in pmz_break_ctl()
729 if (new_reg != uap->curregs[R5]) { in pmz_break_ctl()
730 uap->curregs[R5] = new_reg; in pmz_break_ctl()
731 write_zsreg(uap, R5, uap->curregs[R5]); in pmz_break_ctl()
745 static int pmz_set_scc_power(struct uart_pmac_port *uap, int state) in pmz_set_scc_power() argument
752 PMAC_FTR_SCC_ENABLE, uap->node, uap->port_type, 1); in pmz_set_scc_power()
754 if (ZS_IS_INTMODEM(uap)) { in pmz_set_scc_power()
756 PMAC_FTR_MODEM_ENABLE, uap->node, 0, 1); in pmz_set_scc_power()
764 if (ZS_IS_INTMODEM(uap)) { in pmz_set_scc_power()
766 PMAC_FTR_MODEM_ENABLE, uap->node, 0, 0); in pmz_set_scc_power()
769 pmac_call_feature(PMAC_FTR_SCC_ENABLE, uap->node, uap->port_type, 0); in pmz_set_scc_power()
776 static int pmz_set_scc_power(struct uart_pmac_port *uap, int state) in pmz_set_scc_power() argument
803 static void pmz_fix_zero_bug_scc(struct uart_pmac_port *uap) in pmz_fix_zero_bug_scc() argument
805 write_zsreg(uap, 9, ZS_IS_CHANNEL_A(uap) ? CHRA : CHRB); in pmz_fix_zero_bug_scc()
806 zssync(uap); in pmz_fix_zero_bug_scc()
808 write_zsreg(uap, 9, (ZS_IS_CHANNEL_A(uap) ? CHRA : CHRB) | NV); in pmz_fix_zero_bug_scc()
809 zssync(uap); in pmz_fix_zero_bug_scc()
811 write_zsreg(uap, 4, X1CLK | MONSYNC); in pmz_fix_zero_bug_scc()
812 write_zsreg(uap, 3, Rx8); in pmz_fix_zero_bug_scc()
813 write_zsreg(uap, 5, Tx8 | RTS); in pmz_fix_zero_bug_scc()
814 write_zsreg(uap, 9, NV); /* Didn't we already do this? */ in pmz_fix_zero_bug_scc()
815 write_zsreg(uap, 11, RCBR | TCBR); in pmz_fix_zero_bug_scc()
816 write_zsreg(uap, 12, 0); in pmz_fix_zero_bug_scc()
817 write_zsreg(uap, 13, 0); in pmz_fix_zero_bug_scc()
818 write_zsreg(uap, 14, (LOOPBAK | BRSRC)); in pmz_fix_zero_bug_scc()
819 write_zsreg(uap, 14, (LOOPBAK | BRSRC | BRENAB)); in pmz_fix_zero_bug_scc()
820 write_zsreg(uap, 3, Rx8 | RxENABLE); in pmz_fix_zero_bug_scc()
821 write_zsreg(uap, 0, RES_EXT_INT); in pmz_fix_zero_bug_scc()
822 write_zsreg(uap, 0, RES_EXT_INT); in pmz_fix_zero_bug_scc()
823 write_zsreg(uap, 0, RES_EXT_INT); /* to kill some time */ in pmz_fix_zero_bug_scc()
830 write_zsreg(uap, 9, NV); in pmz_fix_zero_bug_scc()
831 write_zsreg(uap, 4, X16CLK | SB_MASK); in pmz_fix_zero_bug_scc()
832 write_zsreg(uap, 3, Rx8); in pmz_fix_zero_bug_scc()
834 while (read_zsreg(uap, 0) & Rx_CH_AV) { in pmz_fix_zero_bug_scc()
835 (void)read_zsreg(uap, 8); in pmz_fix_zero_bug_scc()
836 write_zsreg(uap, 0, RES_EXT_INT); in pmz_fix_zero_bug_scc()
837 write_zsreg(uap, 0, ERR_RES); in pmz_fix_zero_bug_scc()
847 static int __pmz_startup(struct uart_pmac_port *uap) in __pmz_startup() argument
851 memset(&uap->curregs, 0, sizeof(uap->curregs)); in __pmz_startup()
854 pwr_delay = pmz_set_scc_power(uap, 1); in __pmz_startup()
857 pmz_fix_zero_bug_scc(uap); in __pmz_startup()
860 uap->curregs[R9] = 0; in __pmz_startup()
861 write_zsreg(uap, 9, ZS_IS_CHANNEL_A(uap) ? CHRA : CHRB); in __pmz_startup()
862 zssync(uap); in __pmz_startup()
864 write_zsreg(uap, 9, 0); in __pmz_startup()
865 zssync(uap); in __pmz_startup()
868 write_zsreg(uap, R1, 0); in __pmz_startup()
869 write_zsreg(uap, R0, ERR_RES); in __pmz_startup()
870 write_zsreg(uap, R0, ERR_RES); in __pmz_startup()
871 write_zsreg(uap, R0, RES_H_IUS); in __pmz_startup()
872 write_zsreg(uap, R0, RES_H_IUS); in __pmz_startup()
875 uap->curregs[R4] = X16CLK | SB1; in __pmz_startup()
876 uap->curregs[R3] = Rx8; in __pmz_startup()
877 uap->curregs[R5] = Tx8 | RTS; in __pmz_startup()
878 if (!ZS_IS_IRDA(uap)) in __pmz_startup()
879 uap->curregs[R5] |= DTR; in __pmz_startup()
880 uap->curregs[R12] = 0; in __pmz_startup()
881 uap->curregs[R13] = 0; in __pmz_startup()
882 uap->curregs[R14] = BRENAB; in __pmz_startup()
885 uap->curregs[R15] = BRKIE; in __pmz_startup()
888 uap->curregs[R9] |= NV | MIE; in __pmz_startup()
890 pmz_load_zsregs(uap, uap->curregs); in __pmz_startup()
893 write_zsreg(uap, R3, uap->curregs[R3] |= RxENABLE); in __pmz_startup()
894 write_zsreg(uap, R5, uap->curregs[R5] |= TxENABLE); in __pmz_startup()
897 uap->prev_status = read_zsreg(uap, R0); in __pmz_startup()
902 static void pmz_irda_reset(struct uart_pmac_port *uap) in pmz_irda_reset() argument
906 spin_lock_irqsave(&uap->port.lock, flags); in pmz_irda_reset()
907 uap->curregs[R5] |= DTR; in pmz_irda_reset()
908 write_zsreg(uap, R5, uap->curregs[R5]); in pmz_irda_reset()
909 zssync(uap); in pmz_irda_reset()
910 spin_unlock_irqrestore(&uap->port.lock, flags); in pmz_irda_reset()
913 spin_lock_irqsave(&uap->port.lock, flags); in pmz_irda_reset()
914 uap->curregs[R5] &= ~DTR; in pmz_irda_reset()
915 write_zsreg(uap, R5, uap->curregs[R5]); in pmz_irda_reset()
916 zssync(uap); in pmz_irda_reset()
917 spin_unlock_irqrestore(&uap->port.lock, flags); in pmz_irda_reset()
927 struct uart_pmac_port *uap = to_pmz(port); in pmz_startup() local
933 uap->flags |= PMACZILOG_FLAG_IS_OPEN; in pmz_startup()
938 if (!ZS_IS_CONS(uap)) { in pmz_startup()
940 pwr_delay = __pmz_startup(uap); in pmz_startup()
943 sprintf(uap->irq_name, PMACZILOG_NAME"%d", uap->port.line); in pmz_startup()
944 if (request_irq(uap->port.irq, pmz_interrupt, IRQF_SHARED, in pmz_startup()
945 uap->irq_name, uap)) { in pmz_startup()
947 pmz_set_scc_power(uap, 0); in pmz_startup()
960 if (ZS_IS_IRDA(uap)) in pmz_startup()
961 pmz_irda_reset(uap); in pmz_startup()
965 pmz_interrupt_control(uap, 1); in pmz_startup()
975 struct uart_pmac_port *uap = to_pmz(port); in pmz_shutdown() local
983 pmz_interrupt_control(uap, 0); in pmz_shutdown()
985 if (!ZS_IS_CONS(uap)) { in pmz_shutdown()
987 uap->curregs[R3] &= ~RxENABLE; in pmz_shutdown()
988 uap->curregs[R5] &= ~TxENABLE; in pmz_shutdown()
991 uap->curregs[R5] &= ~SND_BRK; in pmz_shutdown()
992 pmz_maybe_update_regs(uap); in pmz_shutdown()
998 free_irq(uap->port.irq, uap); in pmz_shutdown()
1002 uap->flags &= ~PMACZILOG_FLAG_IS_OPEN; in pmz_shutdown()
1004 if (!ZS_IS_CONS(uap)) in pmz_shutdown()
1005 pmz_set_scc_power(uap, 0); /* Shut the chip down */ in pmz_shutdown()
1015 static void pmz_convert_to_zs(struct uart_pmac_port *uap, unsigned int cflag, in pmz_convert_to_zs() argument
1024 if (baud >= 115200 && ZS_IS_IRDA(uap)) { in pmz_convert_to_zs()
1025 uap->curregs[R4] = X1CLK; in pmz_convert_to_zs()
1026 uap->curregs[R11] = RCTRxCP | TCTRxCP; in pmz_convert_to_zs()
1027 uap->curregs[R14] = 0; /* BRG off */ in pmz_convert_to_zs()
1028 uap->curregs[R12] = 0; in pmz_convert_to_zs()
1029 uap->curregs[R13] = 0; in pmz_convert_to_zs()
1030 uap->flags |= PMACZILOG_FLAG_IS_EXTCLK; in pmz_convert_to_zs()
1034 uap->curregs[R4] = X16CLK; in pmz_convert_to_zs()
1035 uap->curregs[R11] = 0; in pmz_convert_to_zs()
1036 uap->curregs[R14] = 0; in pmz_convert_to_zs()
1039 uap->curregs[R4] = X32CLK; in pmz_convert_to_zs()
1040 uap->curregs[R11] = 0; in pmz_convert_to_zs()
1041 uap->curregs[R14] = 0; in pmz_convert_to_zs()
1044 uap->curregs[R4] = X16CLK; in pmz_convert_to_zs()
1045 uap->curregs[R11] = TCBR | RCBR; in pmz_convert_to_zs()
1047 uap->curregs[R12] = (brg & 255); in pmz_convert_to_zs()
1048 uap->curregs[R13] = ((brg >> 8) & 255); in pmz_convert_to_zs()
1049 uap->curregs[R14] = BRENAB; in pmz_convert_to_zs()
1051 uap->flags &= ~PMACZILOG_FLAG_IS_EXTCLK; in pmz_convert_to_zs()
1055 uap->curregs[3] &= ~RxN_MASK; in pmz_convert_to_zs()
1056 uap->curregs[5] &= ~TxN_MASK; in pmz_convert_to_zs()
1060 uap->curregs[3] |= Rx5; in pmz_convert_to_zs()
1061 uap->curregs[5] |= Tx5; in pmz_convert_to_zs()
1062 uap->parity_mask = 0x1f; in pmz_convert_to_zs()
1065 uap->curregs[3] |= Rx6; in pmz_convert_to_zs()
1066 uap->curregs[5] |= Tx6; in pmz_convert_to_zs()
1067 uap->parity_mask = 0x3f; in pmz_convert_to_zs()
1070 uap->curregs[3] |= Rx7; in pmz_convert_to_zs()
1071 uap->curregs[5] |= Tx7; in pmz_convert_to_zs()
1072 uap->parity_mask = 0x7f; in pmz_convert_to_zs()
1076 uap->curregs[3] |= Rx8; in pmz_convert_to_zs()
1077 uap->curregs[5] |= Tx8; in pmz_convert_to_zs()
1078 uap->parity_mask = 0xff; in pmz_convert_to_zs()
1081 uap->curregs[4] &= ~(SB_MASK); in pmz_convert_to_zs()
1083 uap->curregs[4] |= SB2; in pmz_convert_to_zs()
1085 uap->curregs[4] |= SB1; in pmz_convert_to_zs()
1087 uap->curregs[4] |= PAR_ENAB; in pmz_convert_to_zs()
1089 uap->curregs[4] &= ~PAR_ENAB; in pmz_convert_to_zs()
1091 uap->curregs[4] |= PAR_EVEN; in pmz_convert_to_zs()
1093 uap->curregs[4] &= ~PAR_EVEN; in pmz_convert_to_zs()
1095 uap->port.read_status_mask = Rx_OVR; in pmz_convert_to_zs()
1097 uap->port.read_status_mask |= CRC_ERR | PAR_ERR; in pmz_convert_to_zs()
1099 uap->port.read_status_mask |= BRK_ABRT; in pmz_convert_to_zs()
1101 uap->port.ignore_status_mask = 0; in pmz_convert_to_zs()
1103 uap->port.ignore_status_mask |= CRC_ERR | PAR_ERR; in pmz_convert_to_zs()
1105 uap->port.ignore_status_mask |= BRK_ABRT; in pmz_convert_to_zs()
1107 uap->port.ignore_status_mask |= Rx_OVR; in pmz_convert_to_zs()
1111 uap->port.ignore_status_mask = 0xff; in pmz_convert_to_zs()
1118 static void pmz_irda_setup(struct uart_pmac_port *uap, unsigned long *baud) in pmz_irda_setup() argument
1163 while ((read_zsreg(uap, R0) & Tx_BUF_EMP) == 0 in pmz_irda_setup()
1164 || (read_zsreg(uap, R1) & ALL_SNT) == 0) { in pmz_irda_setup()
1174 (void)read_zsdata(uap); in pmz_irda_setup()
1175 (void)read_zsdata(uap); in pmz_irda_setup()
1176 (void)read_zsdata(uap); in pmz_irda_setup()
1178 while (read_zsreg(uap, R0) & Rx_CH_AV) { in pmz_irda_setup()
1179 read_zsdata(uap); in pmz_irda_setup()
1188 uap->curregs[R5] |= DTR; in pmz_irda_setup()
1189 write_zsreg(uap, R5, uap->curregs[R5]); in pmz_irda_setup()
1190 zssync(uap); in pmz_irda_setup()
1194 pmz_convert_to_zs(uap, CS8, 0, 19200); in pmz_irda_setup()
1195 pmz_load_zsregs(uap, uap->curregs); in pmz_irda_setup()
1199 write_zsdata(uap, 1); in pmz_irda_setup()
1201 while ((read_zsreg(uap, R0) & Rx_CH_AV) == 0) { in pmz_irda_setup()
1208 version = read_zsdata(uap); in pmz_irda_setup()
1216 write_zsdata(uap, cmdbyte); in pmz_irda_setup()
1218 while ((read_zsreg(uap, R0) & Rx_CH_AV) == 0) { in pmz_irda_setup()
1225 t = read_zsdata(uap); in pmz_irda_setup()
1232 (void)read_zsdata(uap); in pmz_irda_setup()
1233 (void)read_zsdata(uap); in pmz_irda_setup()
1234 (void)read_zsdata(uap); in pmz_irda_setup()
1238 uap->curregs[R5] &= ~DTR; in pmz_irda_setup()
1239 write_zsreg(uap, R5, uap->curregs[R5]); in pmz_irda_setup()
1240 zssync(uap); in pmz_irda_setup()
1242 (void)read_zsdata(uap); in pmz_irda_setup()
1243 (void)read_zsdata(uap); in pmz_irda_setup()
1244 (void)read_zsdata(uap); in pmz_irda_setup()
1251 struct uart_pmac_port *uap = to_pmz(port); in __pmz_set_termios() local
1256 memcpy(&uap->termios_cache, termios, sizeof(struct ktermios)); in __pmz_set_termios()
1265 if (ZS_IS_IRDA(uap)) { in __pmz_set_termios()
1270 pmz_irda_setup(uap, &baud); in __pmz_set_termios()
1272 pmz_convert_to_zs(uap, termios->c_cflag, termios->c_iflag, baud); in __pmz_set_termios()
1273 pmz_load_zsregs(uap, uap->curregs); in __pmz_set_termios()
1274 zssync(uap); in __pmz_set_termios()
1277 pmz_convert_to_zs(uap, termios->c_cflag, termios->c_iflag, baud); in __pmz_set_termios()
1279 if (UART_ENABLE_MS(&uap->port, termios->c_cflag)) { in __pmz_set_termios()
1280 uap->curregs[R15] |= DCDIE | SYNCIE | CTSIE; in __pmz_set_termios()
1281 uap->flags |= PMACZILOG_FLAG_MODEM_STATUS; in __pmz_set_termios()
1283 uap->curregs[R15] &= ~(DCDIE | SYNCIE | CTSIE); in __pmz_set_termios()
1284 uap->flags &= ~PMACZILOG_FLAG_MODEM_STATUS; in __pmz_set_termios()
1288 pmz_maybe_update_regs(uap); in __pmz_set_termios()
1299 struct uart_pmac_port *uap = to_pmz(port); in pmz_set_termios() local
1305 pmz_interrupt_control(uap, 0); in pmz_set_termios()
1311 if (ZS_IS_OPEN(uap)) in pmz_set_termios()
1312 pmz_interrupt_control(uap, 1); in pmz_set_termios()
1319 struct uart_pmac_port *uap = to_pmz(port); in pmz_type() local
1321 if (ZS_IS_IRDA(uap)) in pmz_type()
1323 else if (ZS_IS_INTMODEM(uap)) in pmz_type()
1355 struct uart_pmac_port *uap = in pmz_poll_get_char() local
1360 if ((read_zsreg(uap, R0) & Rx_CH_AV) != 0) in pmz_poll_get_char()
1361 return read_zsdata(uap); in pmz_poll_get_char()
1371 struct uart_pmac_port *uap = in pmz_poll_put_char() local
1375 while ((read_zsreg(uap, R0) & Tx_BUF_EMP) == 0) in pmz_poll_put_char()
1377 write_zsdata(uap, c); in pmz_poll_put_char()
1412 static int __init pmz_init_port(struct uart_pmac_port *uap) in pmz_init_port() argument
1414 struct device_node *np = uap->node; in pmz_init_port()
1428 uap->port.mapbase = r_ports.start; in pmz_init_port()
1429 uap->port.membase = ioremap(uap->port.mapbase, 0x1000); in pmz_init_port()
1431 uap->control_reg = uap->port.membase; in pmz_init_port()
1432 uap->data_reg = uap->control_reg + 0x10; in pmz_init_port()
1440 uap->flags |= PMACZILOG_FLAG_HAS_DMA; in pmz_init_port()
1445 if (ZS_HAS_DMA(uap)) { in pmz_init_port()
1446 uap->tx_dma_regs = ioremap(r_txdma.start, 0x100); in pmz_init_port()
1447 if (uap->tx_dma_regs == NULL) { in pmz_init_port()
1448 uap->flags &= ~PMACZILOG_FLAG_HAS_DMA; in pmz_init_port()
1451 uap->rx_dma_regs = ioremap(r_rxdma.start, 0x100); in pmz_init_port()
1452 if (uap->rx_dma_regs == NULL) { in pmz_init_port()
1453 iounmap(uap->tx_dma_regs); in pmz_init_port()
1454 uap->tx_dma_regs = NULL; in pmz_init_port()
1455 uap->flags &= ~PMACZILOG_FLAG_HAS_DMA; in pmz_init_port()
1458 uap->tx_dma_irq = irq_of_parse_and_map(np, 1); in pmz_init_port()
1459 uap->rx_dma_irq = irq_of_parse_and_map(np, 2); in pmz_init_port()
1467 uap->flags |= PMACZILOG_FLAG_IS_INTMODEM; in pmz_init_port()
1470 uap->flags |= PMACZILOG_FLAG_IS_IRDA; in pmz_init_port()
1471 uap->port_type = PMAC_SCC_ASYNC; in pmz_init_port()
1476 uap->flags |= PMACZILOG_FLAG_IS_IRDA; in pmz_init_port()
1478 uap->flags |= PMACZILOG_FLAG_IS_INTMODEM; in pmz_init_port()
1480 if (ZS_IS_IRDA(uap)) in pmz_init_port()
1481 uap->port_type = PMAC_SCC_IRDA; in pmz_init_port()
1482 if (ZS_IS_INTMODEM(uap)) { in pmz_init_port()
1495 uap->port_type = PMAC_SCC_I2S1; in pmz_init_port()
1508 uap->port.iotype = UPIO_MEM; in pmz_init_port()
1509 uap->port.irq = irq_of_parse_and_map(np, 0); in pmz_init_port()
1510 uap->port.uartclk = ZS_CLOCK; in pmz_init_port()
1511 uap->port.fifosize = 1; in pmz_init_port()
1512 uap->port.ops = &pmz_pops; in pmz_init_port()
1513 uap->port.type = PORT_PMAC_ZILOG; in pmz_init_port()
1514 uap->port.flags = 0; in pmz_init_port()
1522 if (uap->port.irq == 0 && in pmz_init_port()
1526 uap->port.irq = irq_create_mapping(NULL, 64 + 15); in pmz_init_port()
1527 uap->tx_dma_irq = irq_create_mapping(NULL, 64 + 4); in pmz_init_port()
1528 uap->rx_dma_irq = irq_create_mapping(NULL, 64 + 5); in pmz_init_port()
1535 pmz_convert_to_zs(uap, CS8, 0, 9600); in pmz_init_port()
1543 static void pmz_dispose_port(struct uart_pmac_port *uap) in pmz_dispose_port() argument
1547 np = uap->node; in pmz_dispose_port()
1548 iounmap(uap->rx_dma_regs); in pmz_dispose_port()
1549 iounmap(uap->tx_dma_regs); in pmz_dispose_port()
1550 iounmap(uap->control_reg); in pmz_dispose_port()
1551 uap->node = NULL; in pmz_dispose_port()
1553 memset(uap, 0, sizeof(struct uart_pmac_port)); in pmz_dispose_port()
1561 struct uart_pmac_port *uap; in pmz_attach() local
1573 uap = &pmz_ports[i]; in pmz_attach()
1574 uap->dev = mdev; in pmz_attach()
1575 uap->port.dev = &mdev->ofdev.dev; in pmz_attach()
1576 dev_set_drvdata(&mdev->ofdev.dev, uap); in pmz_attach()
1581 if (macio_request_resources(uap->dev, "pmac_zilog")) in pmz_attach()
1584 uap->node->name); in pmz_attach()
1586 uap->flags |= PMACZILOG_FLAG_RSRC_REQUESTED; in pmz_attach()
1588 return uart_add_one_port(&pmz_uart_reg, &uap->port); in pmz_attach()
1597 struct uart_pmac_port *uap = dev_get_drvdata(&mdev->ofdev.dev); in pmz_detach() local
1599 if (!uap) in pmz_detach()
1602 uart_remove_one_port(&pmz_uart_reg, &uap->port); in pmz_detach()
1604 if (uap->flags & PMACZILOG_FLAG_RSRC_REQUESTED) { in pmz_detach()
1605 macio_release_resources(uap->dev); in pmz_detach()
1606 uap->flags &= ~PMACZILOG_FLAG_RSRC_REQUESTED; in pmz_detach()
1609 uap->dev = NULL; in pmz_detach()
1610 uap->port.dev = NULL; in pmz_detach()
1618 struct uart_pmac_port *uap = dev_get_drvdata(&mdev->ofdev.dev); in pmz_suspend() local
1620 if (uap == NULL) { in pmz_suspend()
1625 uart_suspend_port(&pmz_uart_reg, &uap->port); in pmz_suspend()
1633 struct uart_pmac_port *uap = dev_get_drvdata(&mdev->ofdev.dev); in pmz_resume() local
1635 if (uap == NULL) in pmz_resume()
1638 uart_resume_port(&pmz_uart_reg, &uap->port); in pmz_resume()
1716 static int __init pmz_init_port(struct uart_pmac_port *uap) in pmz_init_port() argument
1721 r_ports = platform_get_resource(uap->pdev, IORESOURCE_MEM, 0); in pmz_init_port()
1722 irq = platform_get_irq(uap->pdev, 0); in pmz_init_port()
1726 uap->port.mapbase = r_ports->start; in pmz_init_port()
1727 uap->port.membase = (unsigned char __iomem *) r_ports->start; in pmz_init_port()
1728 uap->port.iotype = UPIO_MEM; in pmz_init_port()
1729 uap->port.irq = irq; in pmz_init_port()
1730 uap->port.uartclk = ZS_CLOCK; in pmz_init_port()
1731 uap->port.fifosize = 1; in pmz_init_port()
1732 uap->port.ops = &pmz_pops; in pmz_init_port()
1733 uap->port.type = PORT_PMAC_ZILOG; in pmz_init_port()
1734 uap->port.flags = 0; in pmz_init_port()
1736 uap->control_reg = uap->port.membase; in pmz_init_port()
1737 uap->data_reg = uap->control_reg + 4; in pmz_init_port()
1738 uap->port_type = 0; in pmz_init_port()
1740 pmz_convert_to_zs(uap, CS8, 0, 9600); in pmz_init_port()
1772 static void pmz_dispose_port(struct uart_pmac_port *uap) in pmz_dispose_port() argument
1774 memset(uap, 0, sizeof(struct uart_pmac_port)); in pmz_dispose_port()
1779 struct uart_pmac_port *uap; in pmz_attach() local
1789 uap = &pmz_ports[i]; in pmz_attach()
1790 uap->port.dev = &pdev->dev; in pmz_attach()
1791 platform_set_drvdata(pdev, uap); in pmz_attach()
1793 return uart_add_one_port(&pmz_uart_reg, &uap->port); in pmz_attach()
1798 struct uart_pmac_port *uap = platform_get_drvdata(pdev); in pmz_detach() local
1800 if (!uap) in pmz_detach()
1803 uart_remove_one_port(&pmz_uart_reg, &uap->port); in pmz_detach()
1805 uap->port.dev = NULL; in pmz_detach()
1958 struct uart_pmac_port *uap = in pmz_console_putchar() local
1962 while ((read_zsreg(uap, R0) & Tx_BUF_EMP) == 0) in pmz_console_putchar()
1964 write_zsdata(uap, ch); in pmz_console_putchar()
1973 struct uart_pmac_port *uap = &pmz_ports[con->index]; in pmz_console_write() local
1976 spin_lock_irqsave(&uap->port.lock, flags); in pmz_console_write()
1979 write_zsreg(uap, R1, uap->curregs[1] & ~TxINT_ENAB); in pmz_console_write()
1980 write_zsreg(uap, R5, uap->curregs[5] | TxENABLE | RTS | DTR); in pmz_console_write()
1982 uart_console_write(&uap->port, s, count, pmz_console_putchar); in pmz_console_write()
1985 write_zsreg(uap, R1, uap->curregs[1]); in pmz_console_write()
1988 spin_unlock_irqrestore(&uap->port.lock, flags); in pmz_console_write()
1996 struct uart_pmac_port *uap; in pmz_console_setup() local
2019 uap = &pmz_ports[co->index]; in pmz_console_setup()
2021 if (uap->node == NULL) in pmz_console_setup()
2024 if (uap->pdev == NULL) in pmz_console_setup()
2027 port = &uap->port; in pmz_console_setup()
2032 uap->flags |= PMACZILOG_FLAG_IS_CONS; in pmz_console_setup()
2042 pwr_delay = __pmz_startup(uap); in pmz_console_setup()