Lines Matching refs:BIT0
496 #define MISC BIT0
515 #define RXSTATUS_DATA_AVAILABLE BIT0
553 #define TXSTATUS_FIFO_EMPTY BIT0
573 #define MISCSTATUS_BRG0_ZERO BIT0
599 #define SICR_BRG0_ZERO BIT0
633 #define TXSTATUS_FIFO_EMPTY BIT0
636 #define DICR_TRANSMIT BIT0
1642 usc_OutDmaReg(info, CDIR, BIT8 | BIT0 ); in mgsl_isr_transmit_dma()
5249 usc_OutReg( info, HCR, (u16)((usc_InReg( info, HCR ) & ~BIT1) | BIT0) ); in usc_enable_loopback()
5312 usc_OutReg( info, HCR, (u16)((usc_InReg( info, HCR ) & ~BIT1) | BIT0) ); in usc_enable_aux_clock()
5318 usc_OutReg( info, HCR, (u16)(usc_InReg( info, HCR ) & ~BIT0) ); in usc_enable_aux_clock()
5648 usc_OutDmaReg( info, DICR, (u16)(usc_InDmaReg(info,DICR) | BIT0) ); in usc_start_transmitter()
6338 (u16)((usc_InReg( info, HCR ) & ~BIT1) | BIT0) ); in usc_enable_async_clock()
6347 usc_OutReg( info, HCR, (u16)(usc_InReg( info, HCR ) & ~BIT0) ); in usc_enable_async_clock()