Lines Matching refs:BIT9
564 #define MISCSTATUS_DSR_LATCHED BIT9
587 #define SICR_DSR_ACTIVE BIT9
589 #define SICR_DSR (BIT9|BIT8)
1598 usc_OutDmaReg( info, CDIR, BIT9 | BIT1 ); in mgsl_isr_receive_dma()
1707 else if ( (DmaVector&(BIT10|BIT9)) == BIT10) in mgsl_interrupt()
4770 RegValue |= BIT9; in usc_set_sdlc_mode()
4772 RegValue |= ( BIT12 | BIT10 | BIT9 ); in usc_set_sdlc_mode()
4845 RegValue |= BIT9 | BIT8; in usc_set_sdlc_mode()
4847 RegValue |= ( BIT12 | BIT10 | BIT9 | BIT8); in usc_set_sdlc_mode()
5016 case HDLC_ENCODING_BIPHASE_SPACE: RegValue |= BIT9; break; in usc_set_sdlc_mode()
5018 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: RegValue |= BIT9 | BIT8; break; in usc_set_sdlc_mode()
5180 case HDLC_PREAMBLE_PATTERN_10: RegValue |= BIT9; break; in usc_set_sdlc_mode()
5181 case HDLC_PREAMBLE_PATTERN_01: RegValue |= BIT9 | BIT8; break; in usc_set_sdlc_mode()