Lines Matching refs:TCR
395 #define TCR 0x82 /* tx control */ macro
1422 value = rd_reg16(info, TCR); in set_break()
1427 wr_reg16(info, TCR, value); in set_break()
2302 unsigned short val = rd_reg16(info, TCR); in isr_txeom()
2303 wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */ in isr_txeom()
2304 wr_reg16(info, TCR, val); /* clear reset bit */ in isr_txeom()
2894 val = rd_reg16(info, TCR); in set_interface()
2899 wr_reg16(info, TCR, val); in set_interface()
4051 wr_reg16(info, TCR, in tx_start()
4052 (unsigned short)((rd_reg16(info, TCR) | BIT1) & ~BIT2)); in tx_start()
4095 val = rd_reg16(info, TCR) & ~BIT1; /* clear enable bit */ in tx_stop()
4096 wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */ in tx_stop()
4182 wr_reg16(info, TCR, val); in async_mode()
4344 wr_reg16(info, TCR, val); in sync_mode()
4506 tcr = rd_reg16(info, TCR); in tx_set_idle()
4516 wr_reg16(info, TCR, tcr); in tx_set_idle()
5005 wr_reg16(info, TCR, in irq_test()
5006 (unsigned short)(rd_reg16(info, TCR) | BIT1)); in irq_test()