428 	wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) | (mask)))
430 	wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) & ~(mask)))
435 static void  wr_reg16(struct slgt_info *info, unsigned int addr, __u16 value);
1427 	wr_reg16(info, TCR, value);  in set_break()
2163 	wr_reg16(info, SSR, status); /* clear pending */  in isr_serial()
2303 		wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */  in isr_txeom()
2304 		wr_reg16(info, TCR, val); /* clear reset bit */  in isr_txeom()
2747 			wr_reg16(info, RCR, rd_reg16(info, RCR) | BIT3);  in rx_enable()
2800 			wr_reg16(info, SCR, (unsigned short)(val | IRQ_RXIDLE));  in wait_mgsl_event()
2863 			wr_reg16(info, SCR,  in wait_mgsl_event()
2899 	wr_reg16(info, TCR, val);  in set_interface()
3884 static void wr_reg16(struct slgt_info *info, unsigned int addr, __u16 value)  in wr_reg16()  function
3936 	wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) | BIT2));  in enable_loopback()
3975 		wr_reg16(info, BDR, (unsigned short)div);  in set_rate()
3985 	wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */  in rx_stop()
3986 	wr_reg16(info, RCR, val);                  /* clear reset bit */  in rx_stop()
3991 	wr_reg16(info, SSR, IRQ_RXIDLE + IRQ_RXOVER);  in rx_stop()
4006 	wr_reg16(info, SSR, IRQ_RXOVER);  in rx_start()
4010 	wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */  in rx_start()
4011 	wr_reg16(info, RCR, val);                  /* clear reset bit */  in rx_start()
4018 		wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) & ~BIT14));  in rx_start()
4026 		wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) | BIT14));  in rx_start()
4042 	wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | BIT1));  in rx_start()
4051 		wr_reg16(info, TCR,  in tx_start()
4072 			wr_reg16(info, SSR, (unsigned short)(IRQ_TXIDLE + IRQ_TXUNDER));  in tx_start()
4077 			wr_reg16(info, SSR, IRQ_TXIDLE);  in tx_start()
4096 	wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */  in tx_stop()
4101 	wr_reg16(info, SSR, (unsigned short)(IRQ_TXIDLE + IRQ_TXUNDER));  in tx_stop()
4182 	wr_reg16(info, TCR, val);  in async_mode()
4219 	wr_reg16(info, RCR, val);  in async_mode()
4265 	wr_reg16(info, SCR, val);  in async_mode()
4344 	wr_reg16(info, TCR, val);  in sync_mode()
4407 	wr_reg16(info, RCR, val);  in sync_mode()
4458 		wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | val));  in sync_mode()
4489 	wr_reg16(info, SCR, BIT15 + BIT14 + BIT0);  in sync_mode()
4516 	wr_reg16(info, TCR, tcr);  in tx_set_idle()
4977 		wr_reg16(info, TIR, patterns[i]);  in register_test()
4978 		wr_reg16(info, BDR, patterns[(i+1)%count]);  in register_test()
5005 	wr_reg16(info, TCR,  in irq_test()
5009 	wr_reg16(info, TDR, 0);  in irq_test()