Lines Matching refs:write_reg
622 static void write_reg(SLMP_INFO *info, unsigned char addr, unsigned char val);
1543 write_reg(info, CTL, RegValue); in set_break()
2086 write_reg(info, IER2, 0); in isr_timer()
2098 write_reg(info, (unsigned char)(timer + TMCS), 0); in isr_timer()
2116 write_reg(info, SR1, status); in isr_rxint()
2119 write_reg(info, SR2, status2); in isr_rxint()
2234 write_reg(info, TXDMA + DIR, 0x00); /* disable Tx DMA IRQs */ in isr_txeom()
2235 write_reg(info, TXDMA + DSR, 0xc0); /* clear IRQs and disable DMA */ in isr_txeom()
2236 write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */ in isr_txeom()
2239 write_reg(info, CMD, TXRESET); in isr_txeom()
2240 write_reg(info, CMD, TXENABLE); in isr_txeom()
2242 write_reg(info, CMD, TXBUFCLR); in isr_txeom()
2248 write_reg(info, SR1, (unsigned char)(UDRN + IDLE)); in isr_txeom()
2293 write_reg(info, SR1, status); in isr_txint()
2340 write_reg(info, IE0, info->ie0_value); in isr_txrdy()
2355 write_reg(info, RXDMA + DSR, (unsigned char)(status | 1)); in isr_rxdmaok()
2372 write_reg(info, RXDMA + DSR, (unsigned char)(status | 1)); in isr_rxdmaerror()
2386 write_reg(info, TXDMA + DIR, 0x00); /* disable Tx DMA IRQs */ in isr_txdmaok()
2387 write_reg(info, TXDMA + DSR, 0xc0); /* clear IRQs and disable DMA */ in isr_txdmaok()
2388 write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */ in isr_txdmaok()
2397 write_reg(info, IE0, info->ie0_value); in isr_txdmaok()
2408 write_reg(info, TXDMA + DSR, (unsigned char)(status | 1)); in isr_txdmaerror()
2446 write_reg(info, IE1, info->ie1_value); in isr_io_pin()
2466 write_reg(info, IE1, info->ie1_value); in isr_io_pin()
2746 write_reg(info, IE1, info->ie1_value); in program_hw()
2996 write_reg(info, IE1, info->ie1_value); /* disable tx status interrupts */ in tx_abort()
2997 write_reg(info, SR1, (unsigned char)(IDLE + UDRN)); /* clear pending */ in tx_abort()
2999 write_reg(info, TXDMA + DSR, 0); /* disable DMA channel */ in tx_abort()
3000 write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */ in tx_abort()
3002 write_reg(info, CMD, TXABORT); in tx_abort()
3078 write_reg(info, IE1, info->ie1_value); in wait_mgsl_event()
3143 write_reg(info, IE1, info->ie1_value); in wait_mgsl_event()
3946 write_reg(info, LPR, 1); /* set low power mode */ in synclinkmp_cleanup()
4035 write_reg(info, MD2, (unsigned char)(read_reg(info, MD2) | (BIT1 + BIT0))); in enable_loopback()
4046 write_reg(info, RXS, 0x40); in enable_loopback()
4047 write_reg(info, TXS, 0x40); in enable_loopback()
4053 write_reg(info, MD2, (unsigned char)(read_reg(info, MD2) & ~(BIT1 + BIT0))); in enable_loopback()
4060 write_reg(info, RXS, 0x00); in enable_loopback()
4061 write_reg(info, TXS, 0x00); in enable_loopback()
4107 write_reg(info, TXS, in set_rate()
4109 write_reg(info, RXS, in set_rate()
4111 write_reg(info, TMC, (unsigned char)TMCValue); in set_rate()
4114 write_reg(info, TXS,0); in set_rate()
4115 write_reg(info, RXS,0); in set_rate()
4116 write_reg(info, TMC, 0); in set_rate()
4128 write_reg(info, CMD, RXRESET); in rx_stop()
4131 write_reg(info, IE0, info->ie0_value); /* disable Rx data interrupts */ in rx_stop()
4133 write_reg(info, RXDMA + DSR, 0); /* disable Rx DMA */ in rx_stop()
4134 write_reg(info, RXDMA + DCMD, SWABORT); /* reset/init Rx DMA */ in rx_stop()
4135 write_reg(info, RXDMA + DIR, 0); /* disable Rx DMA interrupts */ in rx_stop()
4151 write_reg(info, CMD, RXRESET); in rx_start()
4156 write_reg(info, IE0, info->ie0_value); in rx_start()
4159 write_reg(info, RXDMA + DSR, 0); /* disable Rx DMA */ in rx_start()
4160 write_reg(info, RXDMA + DCMD, SWABORT); /* reset/init Rx DMA */ in rx_start()
4183 write_reg(info, RXDMA + DIR, 0x60); /* enable Rx DMA interrupts (EOM/BOF) */ in rx_start()
4184 write_reg(info, RXDMA + DSR, 0xf2); /* clear Rx DMA IRQs, enable Rx DMA */ in rx_start()
4188 write_reg(info, IE0, info->ie0_value); in rx_start()
4191 write_reg(info, CMD, RXENABLE); in rx_start()
4207 write_reg(info, CMD, TXRESET); in tx_start()
4208 write_reg(info, CMD, TXENABLE); in tx_start()
4234 write_reg(info, TXDMA + DSR, 0); /* disable DMA channel */ in tx_start()
4235 write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */ in tx_start()
4248 write_reg(info, IE1, info->ie1_value); in tx_start()
4249 write_reg(info, SR1, (unsigned char)(IDLE + UDRN)); in tx_start()
4251 write_reg(info, TXDMA + DIR, 0x40); /* enable Tx DMA interrupts (EOM) */ in tx_start()
4252 write_reg(info, TXDMA + DSR, 0xf2); /* clear Tx DMA IRQs, enable Tx DMA */ in tx_start()
4261 write_reg(info, IE0, info->ie0_value); in tx_start()
4278 write_reg(info, TXDMA + DSR, 0); /* disable DMA channel */ in tx_stop()
4279 write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */ in tx_stop()
4281 write_reg(info, CMD, TXRESET); in tx_stop()
4284 write_reg(info, IE1, info->ie1_value); /* disable tx status interrupts */ in tx_stop()
4285 write_reg(info, SR1, (unsigned char)(IDLE + UDRN)); /* clear pending */ in tx_stop()
4288 write_reg(info, IE0, info->ie0_value); /* disable tx data interrupts */ in tx_stop()
4331 write_reg(info, TRB, info->x_char); in tx_load_fifo()
4334 write_reg(info, TRB, info->tx_buf[info->tx_get++]); in tx_load_fifo()
4360 write_reg(info, IE0, info->ie0_value); in reset_port()
4361 write_reg(info, IE1, info->ie1_value); in reset_port()
4362 write_reg(info, IE2, info->ie2_value); in reset_port()
4364 write_reg(info, CMD, CHRESET); in reset_port()
4403 write_reg(info, MD0, RegValue); in async_mode()
4425 write_reg(info, MD1, RegValue); in async_mode()
4437 write_reg(info, MD2, RegValue); in async_mode()
4446 write_reg(info, RXS, RegValue); in async_mode()
4455 write_reg(info, TXS, RegValue); in async_mode()
4471 write_reg(info, RRC, 0x00); in async_mode()
4478 write_reg(info, TRC0, 0x10); in async_mode()
4485 write_reg(info, TRC1, 0x1e); in async_mode()
4502 write_reg(info, CTL, RegValue); in async_mode()
4506 write_reg(info, IE0, info->ie0_value); in async_mode()
4510 write_reg(info, IE1, info->ie1_value); in async_mode()
4514 write_reg(info, IE2, info->ie2_value); in async_mode()
4533 write_reg(info, TXDMA + DIR, 0); in hdlc_mode()
4534 write_reg(info, RXDMA + DIR, 0); in hdlc_mode()
4554 write_reg(info, MD0, RegValue); in hdlc_mode()
4566 write_reg(info, MD1, RegValue); in hdlc_mode()
4599 write_reg(info, MD2, RegValue); in hdlc_mode()
4613 write_reg(info, RXS, RegValue); in hdlc_mode()
4626 write_reg(info, TXS, RegValue); in hdlc_mode()
4648 write_reg(info, RRC, rx_active_fifo_level); in hdlc_mode()
4655 write_reg(info, TRC0, tx_active_fifo_level); in hdlc_mode()
4662 write_reg(info, TRC1, (unsigned char)(tx_negate_fifo_level - 1)); in hdlc_mode()
4675 write_reg(info, TXDMA + DMR, 0x14); in hdlc_mode()
4676 write_reg(info, RXDMA + DMR, 0x14); in hdlc_mode()
4679 write_reg(info, RXDMA + CPB, in hdlc_mode()
4683 write_reg(info, TXDMA + CPB, in hdlc_mode()
4690 write_reg(info, IE0, info->ie0_value); in hdlc_mode()
4707 write_reg(info, CTL, RegValue); in hdlc_mode()
4738 write_reg(info, IDL, RegValue); in tx_set_idle()
4782 write_reg(info, CTL, RegValue); in set_signals()
5072 write_reg(info, TMC, testval[i]); in register_test()
5073 write_reg(info, IDL, testval[(i+1)%count]); in register_test()
5074 write_reg(info, SA0, testval[(i+2)%count]); in register_test()
5075 write_reg(info, SA1, testval[(i+3)%count]); in register_test()
5110 write_reg(info, IER2, (unsigned char)((info->port_num & 1) ? BIT6 : BIT4)); in irq_test()
5112 write_reg(info, (unsigned char)(timer + TEPR), 0); /* timer expand prescale */ in irq_test()
5126 write_reg(info, (unsigned char)(timer + TMCS), 0x50); in irq_test()
5147 write_reg(info, PABR0, 0); /* wait controller addr boundary 0 */ in sca_init()
5148 write_reg(info, PABR1, 0); /* wait controller addr boundary 1 */ in sca_init()
5149 write_reg(info, WCRL, 0); /* wait controller low range */ in sca_init()
5150 write_reg(info, WCRM, 0); /* wait controller mid range */ in sca_init()
5151 write_reg(info, WCRH, 0); /* wait controller high range */ in sca_init()
5162 write_reg(info, DPCR, dma_priority); in sca_init()
5165 write_reg(info, DMER, 0x80); in sca_init()
5168 write_reg(info, IER0, 0xff); /* TxRDY,RxRDY,TxINT,RxINT (ports 0-1) */ in sca_init()
5169 write_reg(info, IER1, 0xff); /* DMIB,DMIA (channels 0-3) */ in sca_init()
5170 write_reg(info, IER2, 0xf0); /* TIRQ (timers 0-3) */ in sca_init()
5178 write_reg(info, ITCR, 0); in sca_init()
5560 static void write_reg(SLMP_INFO * info, unsigned char Addr, unsigned char Value) in write_reg() function