97 	struct ci_hdrc				*ci;  member
251 static inline struct ci_role_driver *ci_role(struct ci_hdrc *ci)  in ci_role()  argument
253 	BUG_ON(ci->role >= CI_ROLE_END || !ci->roles[ci->role]);  in ci_role()
254 	return ci->roles[ci->role];  in ci_role()
257 static inline int ci_role_start(struct ci_hdrc *ci, enum ci_role role)  in ci_role_start()  argument
264 	if (!ci->roles[role])  in ci_role_start()
267 	ret = ci->roles[role]->start(ci);  in ci_role_start()
269 		ci->role = role;  in ci_role_start()
273 static inline void ci_role_stop(struct ci_hdrc *ci)  in ci_role_stop()  argument
275 	enum ci_role role = ci->role;  in ci_role_stop()
280 	ci->role = CI_ROLE_END;  in ci_role_stop()
282 	ci->roles[role]->stop(ci);  in ci_role_stop()
293 static inline u32 hw_read_id_reg(struct ci_hdrc *ci, u32 offset, u32 mask)  in hw_read_id_reg()  argument
295 	return ioread32(ci->hw_bank.abs + offset) & mask;  in hw_read_id_reg()
305 static inline void hw_write_id_reg(struct ci_hdrc *ci, u32 offset,  in hw_write_id_reg()  argument
309 		data = (ioread32(ci->hw_bank.abs + offset) & ~mask)  in hw_write_id_reg()
312 	iowrite32(data, ci->hw_bank.abs + offset);  in hw_write_id_reg()
323 static inline u32 hw_read(struct ci_hdrc *ci, enum ci_hw_regs reg, u32 mask)  in hw_read()  argument
325 	return ioread32(ci->hw_bank.regmap[reg]) & mask;  in hw_read()
339 static inline void __hw_write(struct ci_hdrc *ci, u32 val,  in __hw_write()  argument
342 	if (ci->imx28_write_fix)  in __hw_write()
355 static inline void hw_write(struct ci_hdrc *ci, enum ci_hw_regs reg,  in hw_write()  argument
359 		data = (ioread32(ci->hw_bank.regmap[reg]) & ~mask)  in hw_write()
362 	__hw_write(ci, data, ci->hw_bank.regmap[reg]);  in hw_write()
373 static inline u32 hw_test_and_clear(struct ci_hdrc *ci, enum ci_hw_regs reg,  in hw_test_and_clear()  argument
376 	u32 val = ioread32(ci->hw_bank.regmap[reg]) & mask;  in hw_test_and_clear()
378 	__hw_write(ci, val, ci->hw_bank.regmap[reg]);  in hw_test_and_clear()
391 static inline u32 hw_test_and_write(struct ci_hdrc *ci, enum ci_hw_regs reg,  in hw_test_and_write()  argument
394 	u32 val = hw_read(ci, reg, ~0);  in hw_test_and_write()
396 	hw_write(ci, reg, mask, data);  in hw_test_and_write()
406 static inline bool ci_otg_is_fsm_mode(struct ci_hdrc *ci)  in ci_otg_is_fsm_mode()  argument
409 	return ci->is_otg && ci->roles[CI_ROLE_HOST] &&  in ci_otg_is_fsm_mode()
410 					ci->roles[CI_ROLE_GADGET];  in ci_otg_is_fsm_mode()
416 u32 hw_read_intr_enable(struct ci_hdrc *ci);
418 u32 hw_read_intr_status(struct ci_hdrc *ci);
420 int hw_device_reset(struct ci_hdrc *ci);
422 int hw_port_test_set(struct ci_hdrc *ci, u8 mode);
424 u8 hw_port_test_get(struct ci_hdrc *ci);
426 int hw_wait_reg(struct ci_hdrc *ci, enum ci_hw_regs reg, u32 mask,