Lines Matching refs:hsotg
65 static void dwc2_enable_common_interrupts(struct dwc2_hsotg *hsotg) in dwc2_enable_common_interrupts() argument
70 writel(0xffffffff, hsotg->regs + GOTGINT); in dwc2_enable_common_interrupts()
73 writel(0xffffffff, hsotg->regs + GINTSTS); in dwc2_enable_common_interrupts()
78 if (hsotg->core_params->dma_enable <= 0) in dwc2_enable_common_interrupts()
84 writel(intmsk, hsotg->regs + GINTMSK); in dwc2_enable_common_interrupts()
91 static void dwc2_init_fs_ls_pclk_sel(struct dwc2_hsotg *hsotg) in dwc2_init_fs_ls_pclk_sel() argument
95 if ((hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_ULPI && in dwc2_init_fs_ls_pclk_sel()
96 hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED && in dwc2_init_fs_ls_pclk_sel()
97 hsotg->core_params->ulpi_fs_ls > 0) || in dwc2_init_fs_ls_pclk_sel()
98 hsotg->core_params->phy_type == DWC2_PHY_TYPE_PARAM_FS) { in dwc2_init_fs_ls_pclk_sel()
106 dev_dbg(hsotg->dev, "Initializing HCFG.FSLSPClkSel to %08x\n", val); in dwc2_init_fs_ls_pclk_sel()
107 hcfg = readl(hsotg->regs + HCFG); in dwc2_init_fs_ls_pclk_sel()
110 writel(hcfg, hsotg->regs + HCFG); in dwc2_init_fs_ls_pclk_sel()
117 static int dwc2_core_reset(struct dwc2_hsotg *hsotg) in dwc2_core_reset() argument
123 dev_vdbg(hsotg->dev, "%s()\n", __func__); in dwc2_core_reset()
128 greset = readl(hsotg->regs + GRSTCTL); in dwc2_core_reset()
130 dev_warn(hsotg->dev, in dwc2_core_reset()
140 writel(greset, hsotg->regs + GRSTCTL); in dwc2_core_reset()
143 greset = readl(hsotg->regs + GRSTCTL); in dwc2_core_reset()
145 dev_warn(hsotg->dev, in dwc2_core_reset()
152 if (hsotg->dr_mode == USB_DR_MODE_HOST) { in dwc2_core_reset()
153 gusbcfg = readl(hsotg->regs + GUSBCFG); in dwc2_core_reset()
156 writel(gusbcfg, hsotg->regs + GUSBCFG); in dwc2_core_reset()
157 } else if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) { in dwc2_core_reset()
158 gusbcfg = readl(hsotg->regs + GUSBCFG); in dwc2_core_reset()
161 writel(gusbcfg, hsotg->regs + GUSBCFG); in dwc2_core_reset()
162 } else if (hsotg->dr_mode == USB_DR_MODE_OTG) { in dwc2_core_reset()
163 gusbcfg = readl(hsotg->regs + GUSBCFG); in dwc2_core_reset()
166 writel(gusbcfg, hsotg->regs + GUSBCFG); in dwc2_core_reset()
178 static int dwc2_fs_phy_init(struct dwc2_hsotg *hsotg, bool select_phy) in dwc2_fs_phy_init() argument
188 dev_dbg(hsotg->dev, "FS PHY selected\n"); in dwc2_fs_phy_init()
189 usbcfg = readl(hsotg->regs + GUSBCFG); in dwc2_fs_phy_init()
191 writel(usbcfg, hsotg->regs + GUSBCFG); in dwc2_fs_phy_init()
194 retval = dwc2_core_reset(hsotg); in dwc2_fs_phy_init()
196 dev_err(hsotg->dev, "%s() Reset failed, aborting", in dwc2_fs_phy_init()
207 if (dwc2_is_host_mode(hsotg)) in dwc2_fs_phy_init()
208 dwc2_init_fs_ls_pclk_sel(hsotg); in dwc2_fs_phy_init()
210 if (hsotg->core_params->i2c_enable > 0) { in dwc2_fs_phy_init()
211 dev_dbg(hsotg->dev, "FS PHY enabling I2C\n"); in dwc2_fs_phy_init()
214 usbcfg = readl(hsotg->regs + GUSBCFG); in dwc2_fs_phy_init()
216 writel(usbcfg, hsotg->regs + GUSBCFG); in dwc2_fs_phy_init()
219 i2cctl = readl(hsotg->regs + GI2CCTL); in dwc2_fs_phy_init()
223 writel(i2cctl, hsotg->regs + GI2CCTL); in dwc2_fs_phy_init()
225 writel(i2cctl, hsotg->regs + GI2CCTL); in dwc2_fs_phy_init()
231 static int dwc2_hs_phy_init(struct dwc2_hsotg *hsotg, bool select_phy) in dwc2_hs_phy_init() argument
239 usbcfg = readl(hsotg->regs + GUSBCFG); in dwc2_hs_phy_init()
246 switch (hsotg->core_params->phy_type) { in dwc2_hs_phy_init()
249 dev_dbg(hsotg->dev, "HS ULPI PHY selected\n"); in dwc2_hs_phy_init()
252 if (hsotg->core_params->phy_ulpi_ddr > 0) in dwc2_hs_phy_init()
257 dev_dbg(hsotg->dev, "HS UTMI+ PHY selected\n"); in dwc2_hs_phy_init()
259 if (hsotg->core_params->phy_utmi_width == 16) in dwc2_hs_phy_init()
263 dev_err(hsotg->dev, "FS PHY selected at HS!\n"); in dwc2_hs_phy_init()
267 writel(usbcfg, hsotg->regs + GUSBCFG); in dwc2_hs_phy_init()
270 retval = dwc2_core_reset(hsotg); in dwc2_hs_phy_init()
272 dev_err(hsotg->dev, "%s() Reset failed, aborting", in dwc2_hs_phy_init()
280 static int dwc2_phy_init(struct dwc2_hsotg *hsotg, bool select_phy) in dwc2_phy_init() argument
285 if (hsotg->core_params->speed == DWC2_SPEED_PARAM_FULL && in dwc2_phy_init()
286 hsotg->core_params->phy_type == DWC2_PHY_TYPE_PARAM_FS) { in dwc2_phy_init()
288 retval = dwc2_fs_phy_init(hsotg, select_phy); in dwc2_phy_init()
293 retval = dwc2_hs_phy_init(hsotg, select_phy); in dwc2_phy_init()
298 if (hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_ULPI && in dwc2_phy_init()
299 hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED && in dwc2_phy_init()
300 hsotg->core_params->ulpi_fs_ls > 0) { in dwc2_phy_init()
301 dev_dbg(hsotg->dev, "Setting ULPI FSLS\n"); in dwc2_phy_init()
302 usbcfg = readl(hsotg->regs + GUSBCFG); in dwc2_phy_init()
305 writel(usbcfg, hsotg->regs + GUSBCFG); in dwc2_phy_init()
307 usbcfg = readl(hsotg->regs + GUSBCFG); in dwc2_phy_init()
310 writel(usbcfg, hsotg->regs + GUSBCFG); in dwc2_phy_init()
316 static int dwc2_gahbcfg_init(struct dwc2_hsotg *hsotg) in dwc2_gahbcfg_init() argument
318 u32 ahbcfg = readl(hsotg->regs + GAHBCFG); in dwc2_gahbcfg_init()
320 switch (hsotg->hw_params.arch) { in dwc2_gahbcfg_init()
322 dev_err(hsotg->dev, "External DMA Mode not supported\n"); in dwc2_gahbcfg_init()
326 dev_dbg(hsotg->dev, "Internal DMA Mode\n"); in dwc2_gahbcfg_init()
327 if (hsotg->core_params->ahbcfg != -1) { in dwc2_gahbcfg_init()
329 ahbcfg |= hsotg->core_params->ahbcfg & in dwc2_gahbcfg_init()
336 dev_dbg(hsotg->dev, "Slave Only Mode\n"); in dwc2_gahbcfg_init()
340 dev_dbg(hsotg->dev, "dma_enable:%d dma_desc_enable:%d\n", in dwc2_gahbcfg_init()
341 hsotg->core_params->dma_enable, in dwc2_gahbcfg_init()
342 hsotg->core_params->dma_desc_enable); in dwc2_gahbcfg_init()
344 if (hsotg->core_params->dma_enable > 0) { in dwc2_gahbcfg_init()
345 if (hsotg->core_params->dma_desc_enable > 0) in dwc2_gahbcfg_init()
346 dev_dbg(hsotg->dev, "Using Descriptor DMA mode\n"); in dwc2_gahbcfg_init()
348 dev_dbg(hsotg->dev, "Using Buffer DMA mode\n"); in dwc2_gahbcfg_init()
350 dev_dbg(hsotg->dev, "Using Slave mode\n"); in dwc2_gahbcfg_init()
351 hsotg->core_params->dma_desc_enable = 0; in dwc2_gahbcfg_init()
354 if (hsotg->core_params->dma_enable > 0) in dwc2_gahbcfg_init()
357 writel(ahbcfg, hsotg->regs + GAHBCFG); in dwc2_gahbcfg_init()
362 static void dwc2_gusbcfg_init(struct dwc2_hsotg *hsotg) in dwc2_gusbcfg_init() argument
366 usbcfg = readl(hsotg->regs + GUSBCFG); in dwc2_gusbcfg_init()
369 switch (hsotg->hw_params.op_mode) { in dwc2_gusbcfg_init()
371 if (hsotg->core_params->otg_cap == in dwc2_gusbcfg_init()
374 if (hsotg->core_params->otg_cap != in dwc2_gusbcfg_init()
382 if (hsotg->core_params->otg_cap != in dwc2_gusbcfg_init()
394 writel(usbcfg, hsotg->regs + GUSBCFG); in dwc2_gusbcfg_init()
405 int dwc2_core_init(struct dwc2_hsotg *hsotg, bool select_phy, int irq) in dwc2_core_init() argument
410 dev_dbg(hsotg->dev, "%s(%p)\n", __func__, hsotg); in dwc2_core_init()
412 usbcfg = readl(hsotg->regs + GUSBCFG); in dwc2_core_init()
416 if (hsotg->core_params->phy_ulpi_ext_vbus == in dwc2_core_init()
422 if (hsotg->core_params->ts_dline > 0) in dwc2_core_init()
425 writel(usbcfg, hsotg->regs + GUSBCFG); in dwc2_core_init()
428 retval = dwc2_core_reset(hsotg); in dwc2_core_init()
430 dev_err(hsotg->dev, "%s(): Reset failed, aborting\n", in dwc2_core_init()
438 retval = dwc2_phy_init(hsotg, select_phy); in dwc2_core_init()
443 retval = dwc2_gahbcfg_init(hsotg); in dwc2_core_init()
448 dwc2_gusbcfg_init(hsotg); in dwc2_core_init()
451 otgctl = readl(hsotg->regs + GOTGCTL); in dwc2_core_init()
453 if (hsotg->core_params->otg_ver > 0) in dwc2_core_init()
455 writel(otgctl, hsotg->regs + GOTGCTL); in dwc2_core_init()
456 dev_dbg(hsotg->dev, "OTG VER PARAM: %d\n", hsotg->core_params->otg_ver); in dwc2_core_init()
459 hsotg->srp_success = 0; in dwc2_core_init()
462 dwc2_enable_common_interrupts(hsotg); in dwc2_core_init()
468 if (dwc2_is_host_mode(hsotg)) { in dwc2_core_init()
469 dev_dbg(hsotg->dev, "Host Mode\n"); in dwc2_core_init()
470 hsotg->op_state = OTG_STATE_A_HOST; in dwc2_core_init()
472 dev_dbg(hsotg->dev, "Device Mode\n"); in dwc2_core_init()
473 hsotg->op_state = OTG_STATE_B_PERIPHERAL; in dwc2_core_init()
484 void dwc2_enable_host_interrupts(struct dwc2_hsotg *hsotg) in dwc2_enable_host_interrupts() argument
488 dev_dbg(hsotg->dev, "%s()\n", __func__); in dwc2_enable_host_interrupts()
491 writel(0, hsotg->regs + GINTMSK); in dwc2_enable_host_interrupts()
492 writel(0, hsotg->regs + HAINTMSK); in dwc2_enable_host_interrupts()
495 dwc2_enable_common_interrupts(hsotg); in dwc2_enable_host_interrupts()
498 intmsk = readl(hsotg->regs + GINTMSK); in dwc2_enable_host_interrupts()
500 writel(intmsk, hsotg->regs + GINTMSK); in dwc2_enable_host_interrupts()
508 void dwc2_disable_host_interrupts(struct dwc2_hsotg *hsotg) in dwc2_disable_host_interrupts() argument
510 u32 intmsk = readl(hsotg->regs + GINTMSK); in dwc2_disable_host_interrupts()
515 writel(intmsk, hsotg->regs + GINTMSK); in dwc2_disable_host_interrupts()
525 static void dwc2_calculate_dynamic_fifo(struct dwc2_hsotg *hsotg) in dwc2_calculate_dynamic_fifo() argument
527 struct dwc2_core_params *params = hsotg->core_params; in dwc2_calculate_dynamic_fifo()
528 struct dwc2_hw_params *hw = &hsotg->hw_params; in dwc2_calculate_dynamic_fifo()
581 dev_err(hsotg->dev, "invalid fifo sizes\n"); in dwc2_calculate_dynamic_fifo()
584 static void dwc2_config_fifos(struct dwc2_hsotg *hsotg) in dwc2_config_fifos() argument
586 struct dwc2_core_params *params = hsotg->core_params; in dwc2_config_fifos()
592 dwc2_calculate_dynamic_fifo(hsotg); in dwc2_config_fifos()
595 grxfsiz = readl(hsotg->regs + GRXFSIZ); in dwc2_config_fifos()
596 dev_dbg(hsotg->dev, "initial grxfsiz=%08x\n", grxfsiz); in dwc2_config_fifos()
600 writel(grxfsiz, hsotg->regs + GRXFSIZ); in dwc2_config_fifos()
601 dev_dbg(hsotg->dev, "new grxfsiz=%08x\n", readl(hsotg->regs + GRXFSIZ)); in dwc2_config_fifos()
604 dev_dbg(hsotg->dev, "initial gnptxfsiz=%08x\n", in dwc2_config_fifos()
605 readl(hsotg->regs + GNPTXFSIZ)); in dwc2_config_fifos()
610 writel(nptxfsiz, hsotg->regs + GNPTXFSIZ); in dwc2_config_fifos()
611 dev_dbg(hsotg->dev, "new gnptxfsiz=%08x\n", in dwc2_config_fifos()
612 readl(hsotg->regs + GNPTXFSIZ)); in dwc2_config_fifos()
615 dev_dbg(hsotg->dev, "initial hptxfsiz=%08x\n", in dwc2_config_fifos()
616 readl(hsotg->regs + HPTXFSIZ)); in dwc2_config_fifos()
622 writel(hptxfsiz, hsotg->regs + HPTXFSIZ); in dwc2_config_fifos()
623 dev_dbg(hsotg->dev, "new hptxfsiz=%08x\n", in dwc2_config_fifos()
624 readl(hsotg->regs + HPTXFSIZ)); in dwc2_config_fifos()
626 if (hsotg->core_params->en_multiple_tx_fifo > 0 && in dwc2_config_fifos()
627 hsotg->hw_params.snpsid <= DWC2_CORE_REV_2_94a) { in dwc2_config_fifos()
632 dfifocfg = readl(hsotg->regs + GDFIFOCFG); in dwc2_config_fifos()
639 writel(dfifocfg, hsotg->regs + GDFIFOCFG); in dwc2_config_fifos()
653 void dwc2_core_host_init(struct dwc2_hsotg *hsotg) in dwc2_core_host_init() argument
657 dev_dbg(hsotg->dev, "%s(%p)\n", __func__, hsotg); in dwc2_core_host_init()
660 writel(0, hsotg->regs + PCGCTL); in dwc2_core_host_init()
663 dwc2_init_fs_ls_pclk_sel(hsotg); in dwc2_core_host_init()
664 if (hsotg->core_params->speed == DWC2_SPEED_PARAM_FULL) { in dwc2_core_host_init()
665 hcfg = readl(hsotg->regs + HCFG); in dwc2_core_host_init()
667 writel(hcfg, hsotg->regs + HCFG); in dwc2_core_host_init()
675 if (hsotg->core_params->reload_ctl > 0) { in dwc2_core_host_init()
676 hfir = readl(hsotg->regs + HFIR); in dwc2_core_host_init()
678 writel(hfir, hsotg->regs + HFIR); in dwc2_core_host_init()
681 if (hsotg->core_params->dma_desc_enable > 0) { in dwc2_core_host_init()
682 u32 op_mode = hsotg->hw_params.op_mode; in dwc2_core_host_init()
683 if (hsotg->hw_params.snpsid < DWC2_CORE_REV_2_90a || in dwc2_core_host_init()
684 !hsotg->hw_params.dma_desc_enable || in dwc2_core_host_init()
688 dev_err(hsotg->dev, in dwc2_core_host_init()
690 dev_err(hsotg->dev, in dwc2_core_host_init()
692 hsotg->core_params->dma_desc_enable = 0; in dwc2_core_host_init()
694 hcfg = readl(hsotg->regs + HCFG); in dwc2_core_host_init()
696 writel(hcfg, hsotg->regs + HCFG); in dwc2_core_host_init()
701 dwc2_config_fifos(hsotg); in dwc2_core_host_init()
705 otgctl = readl(hsotg->regs + GOTGCTL); in dwc2_core_host_init()
707 writel(otgctl, hsotg->regs + GOTGCTL); in dwc2_core_host_init()
710 dwc2_flush_tx_fifo(hsotg, 0x10 /* all TX FIFOs */); in dwc2_core_host_init()
711 dwc2_flush_rx_fifo(hsotg); in dwc2_core_host_init()
714 otgctl = readl(hsotg->regs + GOTGCTL); in dwc2_core_host_init()
716 writel(otgctl, hsotg->regs + GOTGCTL); in dwc2_core_host_init()
718 if (hsotg->core_params->dma_desc_enable <= 0) { in dwc2_core_host_init()
723 num_channels = hsotg->core_params->host_channels; in dwc2_core_host_init()
725 hcchar = readl(hsotg->regs + HCCHAR(i)); in dwc2_core_host_init()
729 writel(hcchar, hsotg->regs + HCCHAR(i)); in dwc2_core_host_init()
736 hcchar = readl(hsotg->regs + HCCHAR(i)); in dwc2_core_host_init()
739 writel(hcchar, hsotg->regs + HCCHAR(i)); in dwc2_core_host_init()
740 dev_dbg(hsotg->dev, "%s: Halt channel %d\n", in dwc2_core_host_init()
743 hcchar = readl(hsotg->regs + HCCHAR(i)); in dwc2_core_host_init()
745 dev_err(hsotg->dev, in dwc2_core_host_init()
756 dev_dbg(hsotg->dev, "Init: Port Power? op_state=%d\n", hsotg->op_state); in dwc2_core_host_init()
757 if (hsotg->op_state == OTG_STATE_A_HOST) { in dwc2_core_host_init()
758 u32 hprt0 = dwc2_read_hprt0(hsotg); in dwc2_core_host_init()
760 dev_dbg(hsotg->dev, "Init: Power Port (%d)\n", in dwc2_core_host_init()
764 writel(hprt0, hsotg->regs + HPRT0); in dwc2_core_host_init()
768 dwc2_enable_host_interrupts(hsotg); in dwc2_core_host_init()
771 static void dwc2_hc_enable_slave_ints(struct dwc2_hsotg *hsotg, in dwc2_hc_enable_slave_ints() argument
779 dev_vdbg(hsotg->dev, "control/bulk\n"); in dwc2_hc_enable_slave_ints()
807 dev_vdbg(hsotg->dev, "intr\n"); in dwc2_hc_enable_slave_ints()
829 dev_vdbg(hsotg->dev, "isoc\n"); in dwc2_hc_enable_slave_ints()
840 dev_err(hsotg->dev, "## Unknown EP type ##\n"); in dwc2_hc_enable_slave_ints()
844 writel(hcintmsk, hsotg->regs + HCINTMSK(chan->hc_num)); in dwc2_hc_enable_slave_ints()
846 dev_vdbg(hsotg->dev, "set HCINTMSK to %08x\n", hcintmsk); in dwc2_hc_enable_slave_ints()
849 static void dwc2_hc_enable_dma_ints(struct dwc2_hsotg *hsotg, in dwc2_hc_enable_dma_ints() argument
858 if (hsotg->core_params->dma_desc_enable <= 0) { in dwc2_hc_enable_dma_ints()
860 dev_vdbg(hsotg->dev, "desc DMA disabled\n"); in dwc2_hc_enable_dma_ints()
864 dev_vdbg(hsotg->dev, "desc DMA enabled\n"); in dwc2_hc_enable_dma_ints()
872 dev_vdbg(hsotg->dev, "setting ACK\n"); in dwc2_hc_enable_dma_ints()
881 writel(hcintmsk, hsotg->regs + HCINTMSK(chan->hc_num)); in dwc2_hc_enable_dma_ints()
883 dev_vdbg(hsotg->dev, "set HCINTMSK to %08x\n", hcintmsk); in dwc2_hc_enable_dma_ints()
886 static void dwc2_hc_enable_ints(struct dwc2_hsotg *hsotg, in dwc2_hc_enable_ints() argument
891 if (hsotg->core_params->dma_enable > 0) { in dwc2_hc_enable_ints()
893 dev_vdbg(hsotg->dev, "DMA enabled\n"); in dwc2_hc_enable_ints()
894 dwc2_hc_enable_dma_ints(hsotg, chan); in dwc2_hc_enable_ints()
897 dev_vdbg(hsotg->dev, "DMA disabled\n"); in dwc2_hc_enable_ints()
898 dwc2_hc_enable_slave_ints(hsotg, chan); in dwc2_hc_enable_ints()
902 intmsk = readl(hsotg->regs + HAINTMSK); in dwc2_hc_enable_ints()
904 writel(intmsk, hsotg->regs + HAINTMSK); in dwc2_hc_enable_ints()
906 dev_vdbg(hsotg->dev, "set HAINTMSK to %08x\n", intmsk); in dwc2_hc_enable_ints()
909 intmsk = readl(hsotg->regs + GINTMSK); in dwc2_hc_enable_ints()
911 writel(intmsk, hsotg->regs + GINTMSK); in dwc2_hc_enable_ints()
913 dev_vdbg(hsotg->dev, "set GINTMSK to %08x\n", intmsk); in dwc2_hc_enable_ints()
927 void dwc2_hc_init(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan) in dwc2_hc_init() argument
935 dev_vdbg(hsotg->dev, "%s()\n", __func__); in dwc2_hc_init()
940 writel(hcintmsk, hsotg->regs + HCINT(hc_num)); in dwc2_hc_init()
943 dwc2_hc_enable_ints(hsotg, chan); in dwc2_hc_init()
957 writel(hcchar, hsotg->regs + HCCHAR(hc_num)); in dwc2_hc_init()
959 dev_vdbg(hsotg->dev, "set HCCHAR(%d) to %08x\n", in dwc2_hc_init()
962 dev_vdbg(hsotg->dev, "%s: Channel %d\n", in dwc2_hc_init()
964 dev_vdbg(hsotg->dev, " Dev Addr: %d\n", in dwc2_hc_init()
966 dev_vdbg(hsotg->dev, " Ep Num: %d\n", in dwc2_hc_init()
968 dev_vdbg(hsotg->dev, " Is In: %d\n", in dwc2_hc_init()
970 dev_vdbg(hsotg->dev, " Is Low Speed: %d\n", in dwc2_hc_init()
972 dev_vdbg(hsotg->dev, " Ep Type: %d\n", in dwc2_hc_init()
974 dev_vdbg(hsotg->dev, " Max Pkt: %d\n", in dwc2_hc_init()
981 dev_vdbg(hsotg->dev, in dwc2_hc_init()
994 dev_vdbg(hsotg->dev, " comp split %d\n", in dwc2_hc_init()
996 dev_vdbg(hsotg->dev, " xact pos %d\n", in dwc2_hc_init()
998 dev_vdbg(hsotg->dev, " hub addr %d\n", in dwc2_hc_init()
1000 dev_vdbg(hsotg->dev, " hub port %d\n", in dwc2_hc_init()
1002 dev_vdbg(hsotg->dev, " is_in %d\n", in dwc2_hc_init()
1004 dev_vdbg(hsotg->dev, " Max Pkt %d\n", in dwc2_hc_init()
1006 dev_vdbg(hsotg->dev, " xferlen %d\n", in dwc2_hc_init()
1011 writel(hcsplt, hsotg->regs + HCSPLT(hc_num)); in dwc2_hc_init()
1042 void dwc2_hc_halt(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan, in dwc2_hc_halt() argument
1048 dev_vdbg(hsotg->dev, "%s()\n", __func__); in dwc2_hc_halt()
1050 dev_err(hsotg->dev, "!!! halt_status = %d !!!\n", halt_status); in dwc2_hc_halt()
1062 dev_vdbg(hsotg->dev, "dequeue/error\n"); in dwc2_hc_halt()
1063 writel(hcintmsk, hsotg->regs + HCINTMSK(chan->hc_num)); in dwc2_hc_halt()
1070 writel(~hcintmsk, hsotg->regs + HCINT(chan->hc_num)); in dwc2_hc_halt()
1079 hcchar = readl(hsotg->regs + HCCHAR(chan->hc_num)); in dwc2_hc_halt()
1101 dev_vdbg(hsotg->dev, in dwc2_hc_halt()
1107 hcchar = readl(hsotg->regs + HCCHAR(chan->hc_num)); in dwc2_hc_halt()
1111 if (hsotg->core_params->dma_desc_enable <= 0) { in dwc2_hc_halt()
1113 dev_vdbg(hsotg->dev, "desc DMA disabled\n"); in dwc2_hc_halt()
1117 dev_dbg(hsotg->dev, "desc DMA enabled\n"); in dwc2_hc_halt()
1121 if (hsotg->core_params->dma_enable <= 0) { in dwc2_hc_halt()
1123 dev_vdbg(hsotg->dev, "DMA not enabled\n"); in dwc2_hc_halt()
1129 dev_vdbg(hsotg->dev, "control/bulk\n"); in dwc2_hc_halt()
1130 nptxsts = readl(hsotg->regs + GNPTXSTS); in dwc2_hc_halt()
1132 dev_vdbg(hsotg->dev, "Disabling channel\n"); in dwc2_hc_halt()
1137 dev_vdbg(hsotg->dev, "isoc/intr\n"); in dwc2_hc_halt()
1138 hptxsts = readl(hsotg->regs + HPTXSTS); in dwc2_hc_halt()
1140 hsotg->queuing_high_bandwidth) { in dwc2_hc_halt()
1142 dev_vdbg(hsotg->dev, "Disabling channel\n"); in dwc2_hc_halt()
1148 dev_vdbg(hsotg->dev, "DMA enabled\n"); in dwc2_hc_halt()
1151 writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num)); in dwc2_hc_halt()
1156 dev_vdbg(hsotg->dev, "Channel enabled\n"); in dwc2_hc_halt()
1161 dev_vdbg(hsotg->dev, "Channel disabled\n"); in dwc2_hc_halt()
1166 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__, in dwc2_hc_halt()
1168 dev_vdbg(hsotg->dev, " hcchar: 0x%08x\n", in dwc2_hc_halt()
1170 dev_vdbg(hsotg->dev, " halt_pending: %d\n", in dwc2_hc_halt()
1172 dev_vdbg(hsotg->dev, " halt_on_queue: %d\n", in dwc2_hc_halt()
1174 dev_vdbg(hsotg->dev, " halt_status: %d\n", in dwc2_hc_halt()
1188 void dwc2_hc_cleanup(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan) in dwc2_hc_cleanup() argument
1198 writel(0, hsotg->regs + HCINTMSK(chan->hc_num)); in dwc2_hc_cleanup()
1201 writel(hcintmsk, hsotg->regs + HCINT(chan->hc_num)); in dwc2_hc_cleanup()
1214 static void dwc2_hc_set_even_odd_frame(struct dwc2_hsotg *hsotg, in dwc2_hc_set_even_odd_frame() argument
1220 if (!(dwc2_hcd_get_frame_number(hsotg) & 0x1)) in dwc2_hc_set_even_odd_frame()
1261 static void dwc2_hc_write_packet(struct dwc2_hsotg *hsotg, in dwc2_hc_write_packet() argument
1272 dev_vdbg(hsotg->dev, "%s()\n", __func__); in dwc2_hc_write_packet()
1274 data_fifo = (u32 __iomem *)(hsotg->regs + HCFIFO(chan->hc_num)); in dwc2_hc_write_packet()
1334 void dwc2_hc_start_transfer(struct dwc2_hsotg *hsotg, in dwc2_hc_start_transfer() argument
1337 u32 max_hc_xfer_size = hsotg->core_params->max_transfer_size; in dwc2_hc_start_transfer()
1338 u16 max_hc_pkt_count = hsotg->core_params->max_packet_count; in dwc2_hc_start_transfer()
1344 dev_vdbg(hsotg->dev, "%s()\n", __func__); in dwc2_hc_start_transfer()
1347 if (hsotg->core_params->dma_enable <= 0) { in dwc2_hc_start_transfer()
1349 dev_vdbg(hsotg->dev, "ping, no DMA\n"); in dwc2_hc_start_transfer()
1350 dwc2_hc_do_ping(hsotg, chan); in dwc2_hc_start_transfer()
1355 dev_vdbg(hsotg->dev, "ping, DMA\n"); in dwc2_hc_start_transfer()
1362 dev_vdbg(hsotg->dev, "split\n"); in dwc2_hc_start_transfer()
1380 dev_vdbg(hsotg->dev, "no split\n"); in dwc2_hc_start_transfer()
1446 writel(hctsiz, hsotg->regs + HCTSIZ(chan->hc_num)); in dwc2_hc_start_transfer()
1448 dev_vdbg(hsotg->dev, "Wrote %08x to HCTSIZ(%d)\n", in dwc2_hc_start_transfer()
1451 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__, in dwc2_hc_start_transfer()
1453 dev_vdbg(hsotg->dev, " Xfer Size: %d\n", in dwc2_hc_start_transfer()
1456 dev_vdbg(hsotg->dev, " Num Pkts: %d\n", in dwc2_hc_start_transfer()
1459 dev_vdbg(hsotg->dev, " Start PID: %d\n", in dwc2_hc_start_transfer()
1464 if (hsotg->core_params->dma_enable > 0) { in dwc2_hc_start_transfer()
1469 dev_vdbg(hsotg->dev, "align_buf\n"); in dwc2_hc_start_transfer()
1474 writel((u32)dma_addr, hsotg->regs + HCDMA(chan->hc_num)); in dwc2_hc_start_transfer()
1476 dev_vdbg(hsotg->dev, "Wrote %08lx to HCDMA(%d)\n", in dwc2_hc_start_transfer()
1482 u32 hcsplt = readl(hsotg->regs + HCSPLT(chan->hc_num)); in dwc2_hc_start_transfer()
1485 writel(hcsplt, hsotg->regs + HCSPLT(chan->hc_num)); in dwc2_hc_start_transfer()
1488 hcchar = readl(hsotg->regs + HCCHAR(chan->hc_num)); in dwc2_hc_start_transfer()
1492 dwc2_hc_set_even_odd_frame(hsotg, chan, &hcchar); in dwc2_hc_start_transfer()
1495 dev_warn(hsotg->dev, in dwc2_hc_start_transfer()
1504 dev_vdbg(hsotg->dev, " Multi Cnt: %d\n", in dwc2_hc_start_transfer()
1508 writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num)); in dwc2_hc_start_transfer()
1510 dev_vdbg(hsotg->dev, "Wrote %08x to HCCHAR(%d)\n", hcchar, in dwc2_hc_start_transfer()
1516 if (hsotg->core_params->dma_enable <= 0 && in dwc2_hc_start_transfer()
1519 dwc2_hc_write_packet(hsotg, chan); in dwc2_hc_start_transfer()
1536 void dwc2_hc_start_transfer_ddma(struct dwc2_hsotg *hsotg, in dwc2_hc_start_transfer_ddma() argument
1560 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__, in dwc2_hc_start_transfer_ddma()
1562 dev_vdbg(hsotg->dev, " Start PID: %d\n", in dwc2_hc_start_transfer_ddma()
1564 dev_vdbg(hsotg->dev, " NTD: %d\n", chan->ntd - 1); in dwc2_hc_start_transfer_ddma()
1567 writel(hctsiz, hsotg->regs + HCTSIZ(chan->hc_num)); in dwc2_hc_start_transfer_ddma()
1573 writel(hc_dma, hsotg->regs + HCDMA(chan->hc_num)); in dwc2_hc_start_transfer_ddma()
1575 dev_vdbg(hsotg->dev, "Wrote %08x to HCDMA(%d)\n", in dwc2_hc_start_transfer_ddma()
1578 hcchar = readl(hsotg->regs + HCCHAR(chan->hc_num)); in dwc2_hc_start_transfer_ddma()
1584 dev_warn(hsotg->dev, in dwc2_hc_start_transfer_ddma()
1593 dev_vdbg(hsotg->dev, " Multi Cnt: %d\n", in dwc2_hc_start_transfer_ddma()
1597 writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num)); in dwc2_hc_start_transfer_ddma()
1599 dev_vdbg(hsotg->dev, "Wrote %08x to HCCHAR(%d)\n", hcchar, in dwc2_hc_start_transfer_ddma()
1626 int dwc2_hc_continue_transfer(struct dwc2_hsotg *hsotg, in dwc2_hc_continue_transfer() argument
1630 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__, in dwc2_hc_continue_transfer()
1654 u32 hcchar = readl(hsotg->regs + HCCHAR(chan->hc_num)); in dwc2_hc_continue_transfer()
1656 dwc2_hc_set_even_odd_frame(hsotg, chan, &hcchar); in dwc2_hc_continue_transfer()
1660 dev_vdbg(hsotg->dev, " IN xfer: hcchar = 0x%08x\n", in dwc2_hc_continue_transfer()
1662 writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num)); in dwc2_hc_continue_transfer()
1672 u32 hcchar = readl(hsotg->regs + in dwc2_hc_continue_transfer()
1675 dwc2_hc_set_even_odd_frame(hsotg, chan, in dwc2_hc_continue_transfer()
1680 dwc2_hc_write_packet(hsotg, chan); in dwc2_hc_continue_transfer()
1697 void dwc2_hc_do_ping(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan) in dwc2_hc_do_ping() argument
1703 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__, in dwc2_hc_do_ping()
1709 writel(hctsiz, hsotg->regs + HCTSIZ(chan->hc_num)); in dwc2_hc_do_ping()
1711 hcchar = readl(hsotg->regs + HCCHAR(chan->hc_num)); in dwc2_hc_do_ping()
1714 writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num)); in dwc2_hc_do_ping()
1727 u32 dwc2_calc_frame_interval(struct dwc2_hsotg *hsotg) in dwc2_calc_frame_interval() argument
1733 usbcfg = readl(hsotg->regs + GUSBCFG); in dwc2_calc_frame_interval()
1734 hprt0 = readl(hsotg->regs + HPRT0); in dwc2_calc_frame_interval()
1739 if ((usbcfg & GUSBCFG_PHYSEL) && hsotg->hw_params.fs_phy_type == in dwc2_calc_frame_interval()
1752 hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_SHARED_UTMI) in dwc2_calc_frame_interval()
1755 hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED) in dwc2_calc_frame_interval()
1774 void dwc2_read_packet(struct dwc2_hsotg *hsotg, u8 *dest, u16 bytes) in dwc2_read_packet() argument
1776 u32 __iomem *fifo = hsotg->regs + HCFIFO(0); in dwc2_read_packet()
1787 dev_vdbg(hsotg->dev, "%s(%p,%p,%d)\n", __func__, hsotg, dest, bytes); in dwc2_read_packet()
1801 void dwc2_dump_host_registers(struct dwc2_hsotg *hsotg) in dwc2_dump_host_registers() argument
1807 dev_dbg(hsotg->dev, "Host Global Registers\n"); in dwc2_dump_host_registers()
1808 addr = hsotg->regs + HCFG; in dwc2_dump_host_registers()
1809 dev_dbg(hsotg->dev, "HCFG @0x%08lX : 0x%08X\n", in dwc2_dump_host_registers()
1811 addr = hsotg->regs + HFIR; in dwc2_dump_host_registers()
1812 dev_dbg(hsotg->dev, "HFIR @0x%08lX : 0x%08X\n", in dwc2_dump_host_registers()
1814 addr = hsotg->regs + HFNUM; in dwc2_dump_host_registers()
1815 dev_dbg(hsotg->dev, "HFNUM @0x%08lX : 0x%08X\n", in dwc2_dump_host_registers()
1817 addr = hsotg->regs + HPTXSTS; in dwc2_dump_host_registers()
1818 dev_dbg(hsotg->dev, "HPTXSTS @0x%08lX : 0x%08X\n", in dwc2_dump_host_registers()
1820 addr = hsotg->regs + HAINT; in dwc2_dump_host_registers()
1821 dev_dbg(hsotg->dev, "HAINT @0x%08lX : 0x%08X\n", in dwc2_dump_host_registers()
1823 addr = hsotg->regs + HAINTMSK; in dwc2_dump_host_registers()
1824 dev_dbg(hsotg->dev, "HAINTMSK @0x%08lX : 0x%08X\n", in dwc2_dump_host_registers()
1826 if (hsotg->core_params->dma_desc_enable > 0) { in dwc2_dump_host_registers()
1827 addr = hsotg->regs + HFLBADDR; in dwc2_dump_host_registers()
1828 dev_dbg(hsotg->dev, "HFLBADDR @0x%08lX : 0x%08X\n", in dwc2_dump_host_registers()
1832 addr = hsotg->regs + HPRT0; in dwc2_dump_host_registers()
1833 dev_dbg(hsotg->dev, "HPRT0 @0x%08lX : 0x%08X\n", in dwc2_dump_host_registers()
1836 for (i = 0; i < hsotg->core_params->host_channels; i++) { in dwc2_dump_host_registers()
1837 dev_dbg(hsotg->dev, "Host Channel %d Specific Registers\n", i); in dwc2_dump_host_registers()
1838 addr = hsotg->regs + HCCHAR(i); in dwc2_dump_host_registers()
1839 dev_dbg(hsotg->dev, "HCCHAR @0x%08lX : 0x%08X\n", in dwc2_dump_host_registers()
1841 addr = hsotg->regs + HCSPLT(i); in dwc2_dump_host_registers()
1842 dev_dbg(hsotg->dev, "HCSPLT @0x%08lX : 0x%08X\n", in dwc2_dump_host_registers()
1844 addr = hsotg->regs + HCINT(i); in dwc2_dump_host_registers()
1845 dev_dbg(hsotg->dev, "HCINT @0x%08lX : 0x%08X\n", in dwc2_dump_host_registers()
1847 addr = hsotg->regs + HCINTMSK(i); in dwc2_dump_host_registers()
1848 dev_dbg(hsotg->dev, "HCINTMSK @0x%08lX : 0x%08X\n", in dwc2_dump_host_registers()
1850 addr = hsotg->regs + HCTSIZ(i); in dwc2_dump_host_registers()
1851 dev_dbg(hsotg->dev, "HCTSIZ @0x%08lX : 0x%08X\n", in dwc2_dump_host_registers()
1853 addr = hsotg->regs + HCDMA(i); in dwc2_dump_host_registers()
1854 dev_dbg(hsotg->dev, "HCDMA @0x%08lX : 0x%08X\n", in dwc2_dump_host_registers()
1856 if (hsotg->core_params->dma_desc_enable > 0) { in dwc2_dump_host_registers()
1857 addr = hsotg->regs + HCDMAB(i); in dwc2_dump_host_registers()
1858 dev_dbg(hsotg->dev, "HCDMAB @0x%08lX : 0x%08X\n", in dwc2_dump_host_registers()
1873 void dwc2_dump_global_registers(struct dwc2_hsotg *hsotg) in dwc2_dump_global_registers() argument
1878 dev_dbg(hsotg->dev, "Core Global Registers\n"); in dwc2_dump_global_registers()
1879 addr = hsotg->regs + GOTGCTL; in dwc2_dump_global_registers()
1880 dev_dbg(hsotg->dev, "GOTGCTL @0x%08lX : 0x%08X\n", in dwc2_dump_global_registers()
1882 addr = hsotg->regs + GOTGINT; in dwc2_dump_global_registers()
1883 dev_dbg(hsotg->dev, "GOTGINT @0x%08lX : 0x%08X\n", in dwc2_dump_global_registers()
1885 addr = hsotg->regs + GAHBCFG; in dwc2_dump_global_registers()
1886 dev_dbg(hsotg->dev, "GAHBCFG @0x%08lX : 0x%08X\n", in dwc2_dump_global_registers()
1888 addr = hsotg->regs + GUSBCFG; in dwc2_dump_global_registers()
1889 dev_dbg(hsotg->dev, "GUSBCFG @0x%08lX : 0x%08X\n", in dwc2_dump_global_registers()
1891 addr = hsotg->regs + GRSTCTL; in dwc2_dump_global_registers()
1892 dev_dbg(hsotg->dev, "GRSTCTL @0x%08lX : 0x%08X\n", in dwc2_dump_global_registers()
1894 addr = hsotg->regs + GINTSTS; in dwc2_dump_global_registers()
1895 dev_dbg(hsotg->dev, "GINTSTS @0x%08lX : 0x%08X\n", in dwc2_dump_global_registers()
1897 addr = hsotg->regs + GINTMSK; in dwc2_dump_global_registers()
1898 dev_dbg(hsotg->dev, "GINTMSK @0x%08lX : 0x%08X\n", in dwc2_dump_global_registers()
1900 addr = hsotg->regs + GRXSTSR; in dwc2_dump_global_registers()
1901 dev_dbg(hsotg->dev, "GRXSTSR @0x%08lX : 0x%08X\n", in dwc2_dump_global_registers()
1903 addr = hsotg->regs + GRXFSIZ; in dwc2_dump_global_registers()
1904 dev_dbg(hsotg->dev, "GRXFSIZ @0x%08lX : 0x%08X\n", in dwc2_dump_global_registers()
1906 addr = hsotg->regs + GNPTXFSIZ; in dwc2_dump_global_registers()
1907 dev_dbg(hsotg->dev, "GNPTXFSIZ @0x%08lX : 0x%08X\n", in dwc2_dump_global_registers()
1909 addr = hsotg->regs + GNPTXSTS; in dwc2_dump_global_registers()
1910 dev_dbg(hsotg->dev, "GNPTXSTS @0x%08lX : 0x%08X\n", in dwc2_dump_global_registers()
1912 addr = hsotg->regs + GI2CCTL; in dwc2_dump_global_registers()
1913 dev_dbg(hsotg->dev, "GI2CCTL @0x%08lX : 0x%08X\n", in dwc2_dump_global_registers()
1915 addr = hsotg->regs + GPVNDCTL; in dwc2_dump_global_registers()
1916 dev_dbg(hsotg->dev, "GPVNDCTL @0x%08lX : 0x%08X\n", in dwc2_dump_global_registers()
1918 addr = hsotg->regs + GGPIO; in dwc2_dump_global_registers()
1919 dev_dbg(hsotg->dev, "GGPIO @0x%08lX : 0x%08X\n", in dwc2_dump_global_registers()
1921 addr = hsotg->regs + GUID; in dwc2_dump_global_registers()
1922 dev_dbg(hsotg->dev, "GUID @0x%08lX : 0x%08X\n", in dwc2_dump_global_registers()
1924 addr = hsotg->regs + GSNPSID; in dwc2_dump_global_registers()
1925 dev_dbg(hsotg->dev, "GSNPSID @0x%08lX : 0x%08X\n", in dwc2_dump_global_registers()
1927 addr = hsotg->regs + GHWCFG1; in dwc2_dump_global_registers()
1928 dev_dbg(hsotg->dev, "GHWCFG1 @0x%08lX : 0x%08X\n", in dwc2_dump_global_registers()
1930 addr = hsotg->regs + GHWCFG2; in dwc2_dump_global_registers()
1931 dev_dbg(hsotg->dev, "GHWCFG2 @0x%08lX : 0x%08X\n", in dwc2_dump_global_registers()
1933 addr = hsotg->regs + GHWCFG3; in dwc2_dump_global_registers()
1934 dev_dbg(hsotg->dev, "GHWCFG3 @0x%08lX : 0x%08X\n", in dwc2_dump_global_registers()
1936 addr = hsotg->regs + GHWCFG4; in dwc2_dump_global_registers()
1937 dev_dbg(hsotg->dev, "GHWCFG4 @0x%08lX : 0x%08X\n", in dwc2_dump_global_registers()
1939 addr = hsotg->regs + GLPMCFG; in dwc2_dump_global_registers()
1940 dev_dbg(hsotg->dev, "GLPMCFG @0x%08lX : 0x%08X\n", in dwc2_dump_global_registers()
1942 addr = hsotg->regs + GPWRDN; in dwc2_dump_global_registers()
1943 dev_dbg(hsotg->dev, "GPWRDN @0x%08lX : 0x%08X\n", in dwc2_dump_global_registers()
1945 addr = hsotg->regs + GDFIFOCFG; in dwc2_dump_global_registers()
1946 dev_dbg(hsotg->dev, "GDFIFOCFG @0x%08lX : 0x%08X\n", in dwc2_dump_global_registers()
1948 addr = hsotg->regs + HPTXFSIZ; in dwc2_dump_global_registers()
1949 dev_dbg(hsotg->dev, "HPTXFSIZ @0x%08lX : 0x%08X\n", in dwc2_dump_global_registers()
1952 addr = hsotg->regs + PCGCTL; in dwc2_dump_global_registers()
1953 dev_dbg(hsotg->dev, "PCGCTL @0x%08lX : 0x%08X\n", in dwc2_dump_global_registers()
1964 void dwc2_flush_tx_fifo(struct dwc2_hsotg *hsotg, const int num) in dwc2_flush_tx_fifo() argument
1969 dev_vdbg(hsotg->dev, "Flush Tx FIFO %d\n", num); in dwc2_flush_tx_fifo()
1973 writel(greset, hsotg->regs + GRSTCTL); in dwc2_flush_tx_fifo()
1976 greset = readl(hsotg->regs + GRSTCTL); in dwc2_flush_tx_fifo()
1978 dev_warn(hsotg->dev, in dwc2_flush_tx_fifo()
1981 readl(hsotg->regs + GNPTXSTS)); in dwc2_flush_tx_fifo()
1996 void dwc2_flush_rx_fifo(struct dwc2_hsotg *hsotg) in dwc2_flush_rx_fifo() argument
2001 dev_vdbg(hsotg->dev, "%s()\n", __func__); in dwc2_flush_rx_fifo()
2004 writel(greset, hsotg->regs + GRSTCTL); in dwc2_flush_rx_fifo()
2007 greset = readl(hsotg->regs + GRSTCTL); in dwc2_flush_rx_fifo()
2009 dev_warn(hsotg->dev, "%s() HANG! GRSTCTL=%0x\n", in dwc2_flush_rx_fifo()
2023 void dwc2_set_param_otg_cap(struct dwc2_hsotg *hsotg, int val) in dwc2_set_param_otg_cap() argument
2029 if (hsotg->hw_params.op_mode != GHWCFG2_OP_MODE_HNP_SRP_CAPABLE) in dwc2_set_param_otg_cap()
2033 switch (hsotg->hw_params.op_mode) { in dwc2_set_param_otg_cap()
2054 dev_err(hsotg->dev, in dwc2_set_param_otg_cap()
2057 switch (hsotg->hw_params.op_mode) { in dwc2_set_param_otg_cap()
2070 dev_dbg(hsotg->dev, "Setting otg_cap to %d\n", val); in dwc2_set_param_otg_cap()
2073 hsotg->core_params->otg_cap = val; in dwc2_set_param_otg_cap()
2076 void dwc2_set_param_dma_enable(struct dwc2_hsotg *hsotg, int val) in dwc2_set_param_dma_enable() argument
2080 if (val > 0 && hsotg->hw_params.arch == GHWCFG2_SLAVE_ONLY_ARCH) in dwc2_set_param_dma_enable()
2087 dev_err(hsotg->dev, in dwc2_set_param_dma_enable()
2090 val = hsotg->hw_params.arch != GHWCFG2_SLAVE_ONLY_ARCH; in dwc2_set_param_dma_enable()
2091 dev_dbg(hsotg->dev, "Setting dma_enable to %d\n", val); in dwc2_set_param_dma_enable()
2094 hsotg->core_params->dma_enable = val; in dwc2_set_param_dma_enable()
2097 void dwc2_set_param_dma_desc_enable(struct dwc2_hsotg *hsotg, int val) in dwc2_set_param_dma_desc_enable() argument
2101 if (val > 0 && (hsotg->core_params->dma_enable <= 0 || in dwc2_set_param_dma_desc_enable()
2102 !hsotg->hw_params.dma_desc_enable)) in dwc2_set_param_dma_desc_enable()
2109 dev_err(hsotg->dev, in dwc2_set_param_dma_desc_enable()
2112 val = (hsotg->core_params->dma_enable > 0 && in dwc2_set_param_dma_desc_enable()
2113 hsotg->hw_params.dma_desc_enable); in dwc2_set_param_dma_desc_enable()
2114 dev_dbg(hsotg->dev, "Setting dma_desc_enable to %d\n", val); in dwc2_set_param_dma_desc_enable()
2117 hsotg->core_params->dma_desc_enable = val; in dwc2_set_param_dma_desc_enable()
2120 void dwc2_set_param_host_support_fs_ls_low_power(struct dwc2_hsotg *hsotg, in dwc2_set_param_host_support_fs_ls_low_power() argument
2125 dev_err(hsotg->dev, in dwc2_set_param_host_support_fs_ls_low_power()
2127 dev_err(hsotg->dev, in dwc2_set_param_host_support_fs_ls_low_power()
2131 dev_dbg(hsotg->dev, in dwc2_set_param_host_support_fs_ls_low_power()
2135 hsotg->core_params->host_support_fs_ls_low_power = val; in dwc2_set_param_host_support_fs_ls_low_power()
2138 void dwc2_set_param_enable_dynamic_fifo(struct dwc2_hsotg *hsotg, int val) in dwc2_set_param_enable_dynamic_fifo() argument
2142 if (val > 0 && !hsotg->hw_params.enable_dynamic_fifo) in dwc2_set_param_enable_dynamic_fifo()
2149 dev_err(hsotg->dev, in dwc2_set_param_enable_dynamic_fifo()
2152 val = hsotg->hw_params.enable_dynamic_fifo; in dwc2_set_param_enable_dynamic_fifo()
2153 dev_dbg(hsotg->dev, "Setting enable_dynamic_fifo to %d\n", val); in dwc2_set_param_enable_dynamic_fifo()
2156 hsotg->core_params->enable_dynamic_fifo = val; in dwc2_set_param_enable_dynamic_fifo()
2159 void dwc2_set_param_host_rx_fifo_size(struct dwc2_hsotg *hsotg, int val) in dwc2_set_param_host_rx_fifo_size() argument
2163 if (val < 16 || val > hsotg->hw_params.host_rx_fifo_size) in dwc2_set_param_host_rx_fifo_size()
2168 dev_err(hsotg->dev, in dwc2_set_param_host_rx_fifo_size()
2171 val = hsotg->hw_params.host_rx_fifo_size; in dwc2_set_param_host_rx_fifo_size()
2172 dev_dbg(hsotg->dev, "Setting host_rx_fifo_size to %d\n", val); in dwc2_set_param_host_rx_fifo_size()
2175 hsotg->core_params->host_rx_fifo_size = val; in dwc2_set_param_host_rx_fifo_size()
2178 void dwc2_set_param_host_nperio_tx_fifo_size(struct dwc2_hsotg *hsotg, int val) in dwc2_set_param_host_nperio_tx_fifo_size() argument
2182 if (val < 16 || val > hsotg->hw_params.host_nperio_tx_fifo_size) in dwc2_set_param_host_nperio_tx_fifo_size()
2187 dev_err(hsotg->dev, in dwc2_set_param_host_nperio_tx_fifo_size()
2190 val = hsotg->hw_params.host_nperio_tx_fifo_size; in dwc2_set_param_host_nperio_tx_fifo_size()
2191 dev_dbg(hsotg->dev, "Setting host_nperio_tx_fifo_size to %d\n", in dwc2_set_param_host_nperio_tx_fifo_size()
2195 hsotg->core_params->host_nperio_tx_fifo_size = val; in dwc2_set_param_host_nperio_tx_fifo_size()
2198 void dwc2_set_param_host_perio_tx_fifo_size(struct dwc2_hsotg *hsotg, int val) in dwc2_set_param_host_perio_tx_fifo_size() argument
2202 if (val < 16 || val > hsotg->hw_params.host_perio_tx_fifo_size) in dwc2_set_param_host_perio_tx_fifo_size()
2207 dev_err(hsotg->dev, in dwc2_set_param_host_perio_tx_fifo_size()
2210 val = hsotg->hw_params.host_perio_tx_fifo_size; in dwc2_set_param_host_perio_tx_fifo_size()
2211 dev_dbg(hsotg->dev, "Setting host_perio_tx_fifo_size to %d\n", in dwc2_set_param_host_perio_tx_fifo_size()
2215 hsotg->core_params->host_perio_tx_fifo_size = val; in dwc2_set_param_host_perio_tx_fifo_size()
2218 void dwc2_set_param_max_transfer_size(struct dwc2_hsotg *hsotg, int val) in dwc2_set_param_max_transfer_size() argument
2222 if (val < 2047 || val > hsotg->hw_params.max_transfer_size) in dwc2_set_param_max_transfer_size()
2227 dev_err(hsotg->dev, in dwc2_set_param_max_transfer_size()
2230 val = hsotg->hw_params.max_transfer_size; in dwc2_set_param_max_transfer_size()
2231 dev_dbg(hsotg->dev, "Setting max_transfer_size to %d\n", val); in dwc2_set_param_max_transfer_size()
2234 hsotg->core_params->max_transfer_size = val; in dwc2_set_param_max_transfer_size()
2237 void dwc2_set_param_max_packet_count(struct dwc2_hsotg *hsotg, int val) in dwc2_set_param_max_packet_count() argument
2241 if (val < 15 || val > hsotg->hw_params.max_packet_count) in dwc2_set_param_max_packet_count()
2246 dev_err(hsotg->dev, in dwc2_set_param_max_packet_count()
2249 val = hsotg->hw_params.max_packet_count; in dwc2_set_param_max_packet_count()
2250 dev_dbg(hsotg->dev, "Setting max_packet_count to %d\n", val); in dwc2_set_param_max_packet_count()
2253 hsotg->core_params->max_packet_count = val; in dwc2_set_param_max_packet_count()
2256 void dwc2_set_param_host_channels(struct dwc2_hsotg *hsotg, int val) in dwc2_set_param_host_channels() argument
2260 if (val < 1 || val > hsotg->hw_params.host_channels) in dwc2_set_param_host_channels()
2265 dev_err(hsotg->dev, in dwc2_set_param_host_channels()
2268 val = hsotg->hw_params.host_channels; in dwc2_set_param_host_channels()
2269 dev_dbg(hsotg->dev, "Setting host_channels to %d\n", val); in dwc2_set_param_host_channels()
2272 hsotg->core_params->host_channels = val; in dwc2_set_param_host_channels()
2275 void dwc2_set_param_phy_type(struct dwc2_hsotg *hsotg, int val) in dwc2_set_param_phy_type() argument
2283 dev_err(hsotg->dev, "Wrong value for phy_type\n"); in dwc2_set_param_phy_type()
2284 dev_err(hsotg->dev, "phy_type must be 0, 1 or 2\n"); in dwc2_set_param_phy_type()
2290 hs_phy_type = hsotg->hw_params.hs_phy_type; in dwc2_set_param_phy_type()
2291 fs_phy_type = hsotg->hw_params.fs_phy_type; in dwc2_set_param_phy_type()
2306 dev_err(hsotg->dev, in dwc2_set_param_phy_type()
2317 dev_dbg(hsotg->dev, "Setting phy_type to %d\n", val); in dwc2_set_param_phy_type()
2320 hsotg->core_params->phy_type = val; in dwc2_set_param_phy_type()
2323 static int dwc2_get_param_phy_type(struct dwc2_hsotg *hsotg) in dwc2_get_param_phy_type() argument
2325 return hsotg->core_params->phy_type; in dwc2_get_param_phy_type()
2328 void dwc2_set_param_speed(struct dwc2_hsotg *hsotg, int val) in dwc2_set_param_speed() argument
2334 dev_err(hsotg->dev, "Wrong value for speed parameter\n"); in dwc2_set_param_speed()
2335 dev_err(hsotg->dev, "max_speed parameter must be 0 or 1\n"); in dwc2_set_param_speed()
2341 dwc2_get_param_phy_type(hsotg) == DWC2_PHY_TYPE_PARAM_FS) in dwc2_set_param_speed()
2346 dev_err(hsotg->dev, in dwc2_set_param_speed()
2349 val = dwc2_get_param_phy_type(hsotg) == DWC2_PHY_TYPE_PARAM_FS ? in dwc2_set_param_speed()
2351 dev_dbg(hsotg->dev, "Setting speed to %d\n", val); in dwc2_set_param_speed()
2354 hsotg->core_params->speed = val; in dwc2_set_param_speed()
2357 void dwc2_set_param_host_ls_low_power_phy_clk(struct dwc2_hsotg *hsotg, int val) in dwc2_set_param_host_ls_low_power_phy_clk() argument
2364 dev_err(hsotg->dev, in dwc2_set_param_host_ls_low_power_phy_clk()
2366 dev_err(hsotg->dev, in dwc2_set_param_host_ls_low_power_phy_clk()
2373 dwc2_get_param_phy_type(hsotg) == DWC2_PHY_TYPE_PARAM_FS) in dwc2_set_param_host_ls_low_power_phy_clk()
2378 dev_err(hsotg->dev, in dwc2_set_param_host_ls_low_power_phy_clk()
2381 val = dwc2_get_param_phy_type(hsotg) == DWC2_PHY_TYPE_PARAM_FS in dwc2_set_param_host_ls_low_power_phy_clk()
2384 dev_dbg(hsotg->dev, "Setting host_ls_low_power_phy_clk to %d\n", in dwc2_set_param_host_ls_low_power_phy_clk()
2388 hsotg->core_params->host_ls_low_power_phy_clk = val; in dwc2_set_param_host_ls_low_power_phy_clk()
2391 void dwc2_set_param_phy_ulpi_ddr(struct dwc2_hsotg *hsotg, int val) in dwc2_set_param_phy_ulpi_ddr() argument
2395 dev_err(hsotg->dev, "Wrong value for phy_ulpi_ddr\n"); in dwc2_set_param_phy_ulpi_ddr()
2396 dev_err(hsotg->dev, "phy_upli_ddr must be 0 or 1\n"); in dwc2_set_param_phy_ulpi_ddr()
2399 dev_dbg(hsotg->dev, "Setting phy_upli_ddr to %d\n", val); in dwc2_set_param_phy_ulpi_ddr()
2402 hsotg->core_params->phy_ulpi_ddr = val; in dwc2_set_param_phy_ulpi_ddr()
2405 void dwc2_set_param_phy_ulpi_ext_vbus(struct dwc2_hsotg *hsotg, int val) in dwc2_set_param_phy_ulpi_ext_vbus() argument
2409 dev_err(hsotg->dev, in dwc2_set_param_phy_ulpi_ext_vbus()
2411 dev_err(hsotg->dev, in dwc2_set_param_phy_ulpi_ext_vbus()
2415 dev_dbg(hsotg->dev, "Setting phy_ulpi_ext_vbus to %d\n", val); in dwc2_set_param_phy_ulpi_ext_vbus()
2418 hsotg->core_params->phy_ulpi_ext_vbus = val; in dwc2_set_param_phy_ulpi_ext_vbus()
2421 void dwc2_set_param_phy_utmi_width(struct dwc2_hsotg *hsotg, int val) in dwc2_set_param_phy_utmi_width() argument
2425 switch (hsotg->hw_params.utmi_phy_data_width) { in dwc2_set_param_phy_utmi_width()
2439 dev_err(hsotg->dev, in dwc2_set_param_phy_utmi_width()
2443 val = (hsotg->hw_params.utmi_phy_data_width == in dwc2_set_param_phy_utmi_width()
2445 dev_dbg(hsotg->dev, "Setting phy_utmi_width to %d\n", val); in dwc2_set_param_phy_utmi_width()
2448 hsotg->core_params->phy_utmi_width = val; in dwc2_set_param_phy_utmi_width()
2451 void dwc2_set_param_ulpi_fs_ls(struct dwc2_hsotg *hsotg, int val) in dwc2_set_param_ulpi_fs_ls() argument
2455 dev_err(hsotg->dev, "Wrong value for ulpi_fs_ls\n"); in dwc2_set_param_ulpi_fs_ls()
2456 dev_err(hsotg->dev, "ulpi_fs_ls must be 0 or 1\n"); in dwc2_set_param_ulpi_fs_ls()
2459 dev_dbg(hsotg->dev, "Setting ulpi_fs_ls to %d\n", val); in dwc2_set_param_ulpi_fs_ls()
2462 hsotg->core_params->ulpi_fs_ls = val; in dwc2_set_param_ulpi_fs_ls()
2465 void dwc2_set_param_ts_dline(struct dwc2_hsotg *hsotg, int val) in dwc2_set_param_ts_dline() argument
2469 dev_err(hsotg->dev, "Wrong value for ts_dline\n"); in dwc2_set_param_ts_dline()
2470 dev_err(hsotg->dev, "ts_dline must be 0 or 1\n"); in dwc2_set_param_ts_dline()
2473 dev_dbg(hsotg->dev, "Setting ts_dline to %d\n", val); in dwc2_set_param_ts_dline()
2476 hsotg->core_params->ts_dline = val; in dwc2_set_param_ts_dline()
2479 void dwc2_set_param_i2c_enable(struct dwc2_hsotg *hsotg, int val) in dwc2_set_param_i2c_enable() argument
2485 dev_err(hsotg->dev, "Wrong value for i2c_enable\n"); in dwc2_set_param_i2c_enable()
2486 dev_err(hsotg->dev, "i2c_enable must be 0 or 1\n"); in dwc2_set_param_i2c_enable()
2492 if (val == 1 && !(hsotg->hw_params.i2c_enable)) in dwc2_set_param_i2c_enable()
2497 dev_err(hsotg->dev, in dwc2_set_param_i2c_enable()
2500 val = hsotg->hw_params.i2c_enable; in dwc2_set_param_i2c_enable()
2501 dev_dbg(hsotg->dev, "Setting i2c_enable to %d\n", val); in dwc2_set_param_i2c_enable()
2504 hsotg->core_params->i2c_enable = val; in dwc2_set_param_i2c_enable()
2507 void dwc2_set_param_en_multiple_tx_fifo(struct dwc2_hsotg *hsotg, int val) in dwc2_set_param_en_multiple_tx_fifo() argument
2513 dev_err(hsotg->dev, in dwc2_set_param_en_multiple_tx_fifo()
2515 dev_err(hsotg->dev, in dwc2_set_param_en_multiple_tx_fifo()
2521 if (val == 1 && !hsotg->hw_params.en_multiple_tx_fifo) in dwc2_set_param_en_multiple_tx_fifo()
2526 dev_err(hsotg->dev, in dwc2_set_param_en_multiple_tx_fifo()
2529 val = hsotg->hw_params.en_multiple_tx_fifo; in dwc2_set_param_en_multiple_tx_fifo()
2530 dev_dbg(hsotg->dev, "Setting en_multiple_tx_fifo to %d\n", val); in dwc2_set_param_en_multiple_tx_fifo()
2533 hsotg->core_params->en_multiple_tx_fifo = val; in dwc2_set_param_en_multiple_tx_fifo()
2536 void dwc2_set_param_reload_ctl(struct dwc2_hsotg *hsotg, int val) in dwc2_set_param_reload_ctl() argument
2542 dev_err(hsotg->dev, in dwc2_set_param_reload_ctl()
2544 dev_err(hsotg->dev, "reload_ctl must be 0 or 1\n"); in dwc2_set_param_reload_ctl()
2549 if (val == 1 && hsotg->hw_params.snpsid < DWC2_CORE_REV_2_92a) in dwc2_set_param_reload_ctl()
2554 dev_err(hsotg->dev, in dwc2_set_param_reload_ctl()
2557 val = hsotg->hw_params.snpsid >= DWC2_CORE_REV_2_92a; in dwc2_set_param_reload_ctl()
2558 dev_dbg(hsotg->dev, "Setting reload_ctl to %d\n", val); in dwc2_set_param_reload_ctl()
2561 hsotg->core_params->reload_ctl = val; in dwc2_set_param_reload_ctl()
2564 void dwc2_set_param_ahbcfg(struct dwc2_hsotg *hsotg, int val) in dwc2_set_param_ahbcfg() argument
2567 hsotg->core_params->ahbcfg = val; in dwc2_set_param_ahbcfg()
2569 hsotg->core_params->ahbcfg = GAHBCFG_HBSTLEN_INCR4 << in dwc2_set_param_ahbcfg()
2573 void dwc2_set_param_otg_ver(struct dwc2_hsotg *hsotg, int val) in dwc2_set_param_otg_ver() argument
2577 dev_err(hsotg->dev, in dwc2_set_param_otg_ver()
2579 dev_err(hsotg->dev, in dwc2_set_param_otg_ver()
2583 dev_dbg(hsotg->dev, "Setting otg_ver to %d\n", val); in dwc2_set_param_otg_ver()
2586 hsotg->core_params->otg_ver = val; in dwc2_set_param_otg_ver()
2589 static void dwc2_set_param_uframe_sched(struct dwc2_hsotg *hsotg, int val) in dwc2_set_param_uframe_sched() argument
2593 dev_err(hsotg->dev, in dwc2_set_param_uframe_sched()
2596 dev_err(hsotg->dev, "uframe_sched must be 0 or 1\n"); in dwc2_set_param_uframe_sched()
2599 dev_dbg(hsotg->dev, "Setting uframe_sched to %d\n", val); in dwc2_set_param_uframe_sched()
2602 hsotg->core_params->uframe_sched = val; in dwc2_set_param_uframe_sched()
2609 void dwc2_set_parameters(struct dwc2_hsotg *hsotg, in dwc2_set_parameters() argument
2612 dev_dbg(hsotg->dev, "%s()\n", __func__); in dwc2_set_parameters()
2614 dwc2_set_param_otg_cap(hsotg, params->otg_cap); in dwc2_set_parameters()
2615 dwc2_set_param_dma_enable(hsotg, params->dma_enable); in dwc2_set_parameters()
2616 dwc2_set_param_dma_desc_enable(hsotg, params->dma_desc_enable); in dwc2_set_parameters()
2617 dwc2_set_param_host_support_fs_ls_low_power(hsotg, in dwc2_set_parameters()
2619 dwc2_set_param_enable_dynamic_fifo(hsotg, in dwc2_set_parameters()
2621 dwc2_set_param_host_rx_fifo_size(hsotg, in dwc2_set_parameters()
2623 dwc2_set_param_host_nperio_tx_fifo_size(hsotg, in dwc2_set_parameters()
2625 dwc2_set_param_host_perio_tx_fifo_size(hsotg, in dwc2_set_parameters()
2627 dwc2_set_param_max_transfer_size(hsotg, in dwc2_set_parameters()
2629 dwc2_set_param_max_packet_count(hsotg, in dwc2_set_parameters()
2631 dwc2_set_param_host_channels(hsotg, params->host_channels); in dwc2_set_parameters()
2632 dwc2_set_param_phy_type(hsotg, params->phy_type); in dwc2_set_parameters()
2633 dwc2_set_param_speed(hsotg, params->speed); in dwc2_set_parameters()
2634 dwc2_set_param_host_ls_low_power_phy_clk(hsotg, in dwc2_set_parameters()
2636 dwc2_set_param_phy_ulpi_ddr(hsotg, params->phy_ulpi_ddr); in dwc2_set_parameters()
2637 dwc2_set_param_phy_ulpi_ext_vbus(hsotg, in dwc2_set_parameters()
2639 dwc2_set_param_phy_utmi_width(hsotg, params->phy_utmi_width); in dwc2_set_parameters()
2640 dwc2_set_param_ulpi_fs_ls(hsotg, params->ulpi_fs_ls); in dwc2_set_parameters()
2641 dwc2_set_param_ts_dline(hsotg, params->ts_dline); in dwc2_set_parameters()
2642 dwc2_set_param_i2c_enable(hsotg, params->i2c_enable); in dwc2_set_parameters()
2643 dwc2_set_param_en_multiple_tx_fifo(hsotg, in dwc2_set_parameters()
2645 dwc2_set_param_reload_ctl(hsotg, params->reload_ctl); in dwc2_set_parameters()
2646 dwc2_set_param_ahbcfg(hsotg, params->ahbcfg); in dwc2_set_parameters()
2647 dwc2_set_param_otg_ver(hsotg, params->otg_ver); in dwc2_set_parameters()
2648 dwc2_set_param_uframe_sched(hsotg, params->uframe_sched); in dwc2_set_parameters()
2655 int dwc2_get_hwparams(struct dwc2_hsotg *hsotg) in dwc2_get_hwparams() argument
2657 struct dwc2_hw_params *hw = &hsotg->hw_params; in dwc2_get_hwparams()
2669 hw->snpsid = readl(hsotg->regs + GSNPSID); in dwc2_get_hwparams()
2672 dev_err(hsotg->dev, "Bad value for GSNPSID: 0x%08x\n", in dwc2_get_hwparams()
2677 dev_dbg(hsotg->dev, "Core Release: %1x.%1x%1x%1x (snpsid=%x)\n", in dwc2_get_hwparams()
2681 hwcfg1 = readl(hsotg->regs + GHWCFG1); in dwc2_get_hwparams()
2682 hwcfg2 = readl(hsotg->regs + GHWCFG2); in dwc2_get_hwparams()
2683 hwcfg3 = readl(hsotg->regs + GHWCFG3); in dwc2_get_hwparams()
2684 hwcfg4 = readl(hsotg->regs + GHWCFG4); in dwc2_get_hwparams()
2685 grxfsiz = readl(hsotg->regs + GRXFSIZ); in dwc2_get_hwparams()
2687 dev_dbg(hsotg->dev, "hwcfg1=%08x\n", hwcfg1); in dwc2_get_hwparams()
2688 dev_dbg(hsotg->dev, "hwcfg2=%08x\n", hwcfg2); in dwc2_get_hwparams()
2689 dev_dbg(hsotg->dev, "hwcfg3=%08x\n", hwcfg3); in dwc2_get_hwparams()
2690 dev_dbg(hsotg->dev, "hwcfg4=%08x\n", hwcfg4); in dwc2_get_hwparams()
2691 dev_dbg(hsotg->dev, "grxfsiz=%08x\n", grxfsiz); in dwc2_get_hwparams()
2694 gusbcfg = readl(hsotg->regs + GUSBCFG); in dwc2_get_hwparams()
2696 writel(gusbcfg, hsotg->regs + GUSBCFG); in dwc2_get_hwparams()
2699 gnptxfsiz = readl(hsotg->regs + GNPTXFSIZ); in dwc2_get_hwparams()
2700 hptxfsiz = readl(hsotg->regs + HPTXFSIZ); in dwc2_get_hwparams()
2701 dev_dbg(hsotg->dev, "gnptxfsiz=%08x\n", gnptxfsiz); in dwc2_get_hwparams()
2702 dev_dbg(hsotg->dev, "hptxfsiz=%08x\n", hptxfsiz); in dwc2_get_hwparams()
2703 gusbcfg = readl(hsotg->regs + GUSBCFG); in dwc2_get_hwparams()
2705 writel(gusbcfg, hsotg->regs + GUSBCFG); in dwc2_get_hwparams()
2767 dev_dbg(hsotg->dev, "Detected values from hardware:\n"); in dwc2_get_hwparams()
2768 dev_dbg(hsotg->dev, " op_mode=%d\n", in dwc2_get_hwparams()
2770 dev_dbg(hsotg->dev, " arch=%d\n", in dwc2_get_hwparams()
2772 dev_dbg(hsotg->dev, " dma_desc_enable=%d\n", in dwc2_get_hwparams()
2774 dev_dbg(hsotg->dev, " power_optimized=%d\n", in dwc2_get_hwparams()
2776 dev_dbg(hsotg->dev, " i2c_enable=%d\n", in dwc2_get_hwparams()
2778 dev_dbg(hsotg->dev, " hs_phy_type=%d\n", in dwc2_get_hwparams()
2780 dev_dbg(hsotg->dev, " fs_phy_type=%d\n", in dwc2_get_hwparams()
2782 dev_dbg(hsotg->dev, " utmi_phy_data_wdith=%d\n", in dwc2_get_hwparams()
2784 dev_dbg(hsotg->dev, " num_dev_ep=%d\n", in dwc2_get_hwparams()
2786 dev_dbg(hsotg->dev, " num_dev_perio_in_ep=%d\n", in dwc2_get_hwparams()
2788 dev_dbg(hsotg->dev, " host_channels=%d\n", in dwc2_get_hwparams()
2790 dev_dbg(hsotg->dev, " max_transfer_size=%d\n", in dwc2_get_hwparams()
2792 dev_dbg(hsotg->dev, " max_packet_count=%d\n", in dwc2_get_hwparams()
2794 dev_dbg(hsotg->dev, " nperio_tx_q_depth=0x%0x\n", in dwc2_get_hwparams()
2796 dev_dbg(hsotg->dev, " host_perio_tx_q_depth=0x%0x\n", in dwc2_get_hwparams()
2798 dev_dbg(hsotg->dev, " dev_token_q_depth=0x%0x\n", in dwc2_get_hwparams()
2800 dev_dbg(hsotg->dev, " enable_dynamic_fifo=%d\n", in dwc2_get_hwparams()
2802 dev_dbg(hsotg->dev, " en_multiple_tx_fifo=%d\n", in dwc2_get_hwparams()
2804 dev_dbg(hsotg->dev, " total_fifo_size=%d\n", in dwc2_get_hwparams()
2806 dev_dbg(hsotg->dev, " host_rx_fifo_size=%d\n", in dwc2_get_hwparams()
2808 dev_dbg(hsotg->dev, " host_nperio_tx_fifo_size=%d\n", in dwc2_get_hwparams()
2810 dev_dbg(hsotg->dev, " host_perio_tx_fifo_size=%d\n", in dwc2_get_hwparams()
2812 dev_dbg(hsotg->dev, "\n"); in dwc2_get_hwparams()
2817 u16 dwc2_get_otg_version(struct dwc2_hsotg *hsotg) in dwc2_get_otg_version() argument
2819 return hsotg->core_params->otg_ver == 1 ? 0x0200 : 0x0103; in dwc2_get_otg_version()
2822 bool dwc2_is_controller_alive(struct dwc2_hsotg *hsotg) in dwc2_is_controller_alive() argument
2824 if (readl(hsotg->regs + GSNPSID) == 0xffffffff) in dwc2_is_controller_alive()
2836 void dwc2_enable_global_interrupts(struct dwc2_hsotg *hsotg) in dwc2_enable_global_interrupts() argument
2838 u32 ahbcfg = readl(hsotg->regs + GAHBCFG); in dwc2_enable_global_interrupts()
2841 writel(ahbcfg, hsotg->regs + GAHBCFG); in dwc2_enable_global_interrupts()
2850 void dwc2_disable_global_interrupts(struct dwc2_hsotg *hsotg) in dwc2_disable_global_interrupts() argument
2852 u32 ahbcfg = readl(hsotg->regs + GAHBCFG); in dwc2_disable_global_interrupts()
2855 writel(ahbcfg, hsotg->regs + GAHBCFG); in dwc2_disable_global_interrupts()