Lines Matching refs:tmp
213 u32 tmp; in udc_mask_unused_interrupts() local
216 tmp = AMD_BIT(UDC_DEVINT_SVC) | in udc_mask_unused_interrupts()
224 writel(tmp, &dev->regs->irqmsk); in udc_mask_unused_interrupts()
235 u32 tmp; in udc_enable_ep0_interrupts() local
240 tmp = readl(&dev->regs->ep_irqmsk); in udc_enable_ep0_interrupts()
242 tmp &= AMD_UNMASK_BIT(UDC_EPINT_IN_EP0) in udc_enable_ep0_interrupts()
244 writel(tmp, &dev->regs->ep_irqmsk); in udc_enable_ep0_interrupts()
252 u32 tmp; in udc_enable_dev_setup_interrupts() local
257 tmp = readl(&dev->regs->irqmsk); in udc_enable_dev_setup_interrupts()
260 tmp &= AMD_UNMASK_BIT(UDC_DEVINT_SI) in udc_enable_dev_setup_interrupts()
265 writel(tmp, &dev->regs->irqmsk); in udc_enable_dev_setup_interrupts()
274 u32 tmp; in udc_set_txfifo_addr() local
287 tmp = readl(&dev->ep[i].regs->bufin_framenum); in udc_set_txfifo_addr()
288 tmp = AMD_GETBITS(tmp, UDC_EPIN_BUFF_SIZE); in udc_set_txfifo_addr()
289 ep->txfifo += tmp; in udc_set_txfifo_addr()
315 u32 tmp; in udc_ep_enable() local
340 tmp = readl(&dev->ep[ep->num].regs->ctl); in udc_ep_enable()
341 tmp = AMD_ADDBITS(tmp, desc->bmAttributes, UDC_EPCTL_ET); in udc_ep_enable()
342 writel(tmp, &dev->ep[ep->num].regs->ctl); in udc_ep_enable()
346 tmp = readl(&dev->ep[ep->num].regs->bufout_maxpkt); in udc_ep_enable()
347 tmp = AMD_ADDBITS(tmp, maxpacket, UDC_EP_MAX_PKT_SIZE); in udc_ep_enable()
349 writel(tmp, &dev->ep[ep->num].regs->bufout_maxpkt); in udc_ep_enable()
358 tmp = readl(&dev->ep[ep->num].regs->bufin_framenum); in udc_ep_enable()
360 tmp = AMD_ADDBITS( in udc_ep_enable()
361 tmp, in udc_ep_enable()
365 writel(tmp, &dev->ep[ep->num].regs->bufin_framenum); in udc_ep_enable()
371 tmp = readl(&ep->regs->ctl); in udc_ep_enable()
372 tmp |= AMD_BIT(UDC_EPCTL_F); in udc_ep_enable()
373 writel(tmp, &ep->regs->ctl); in udc_ep_enable()
381 tmp = readl(&dev->csr->ne[ep->num - UDC_CSR_EP_OUT_IX_OFS]); in udc_ep_enable()
382 tmp = AMD_ADDBITS(tmp, maxpacket, in udc_ep_enable()
384 writel(tmp, &dev->csr->ne[ep->num - UDC_CSR_EP_OUT_IX_OFS]); in udc_ep_enable()
397 tmp = readl(&dev->csr->ne[udc_csr_epix]); in udc_ep_enable()
399 tmp = AMD_ADDBITS(tmp, maxpacket, UDC_CSR_NE_MAX_PKT); in udc_ep_enable()
401 tmp = AMD_ADDBITS(tmp, desc->bEndpointAddress, UDC_CSR_NE_NUM); in udc_ep_enable()
403 tmp = AMD_ADDBITS(tmp, ep->in, UDC_CSR_NE_DIR); in udc_ep_enable()
405 tmp = AMD_ADDBITS(tmp, desc->bmAttributes, UDC_CSR_NE_TYPE); in udc_ep_enable()
407 tmp = AMD_ADDBITS(tmp, ep->dev->cur_config, UDC_CSR_NE_CFG); in udc_ep_enable()
409 tmp = AMD_ADDBITS(tmp, ep->dev->cur_intf, UDC_CSR_NE_INTF); in udc_ep_enable()
411 tmp = AMD_ADDBITS(tmp, ep->dev->cur_alt, UDC_CSR_NE_ALT); in udc_ep_enable()
413 writel(tmp, &dev->csr->ne[udc_csr_epix]); in udc_ep_enable()
416 tmp = readl(&dev->regs->ep_irqmsk); in udc_ep_enable()
417 tmp &= AMD_UNMASK_BIT(ep->num); in udc_ep_enable()
418 writel(tmp, &dev->regs->ep_irqmsk); in udc_ep_enable()
425 tmp = readl(&ep->regs->ctl); in udc_ep_enable()
426 tmp |= AMD_BIT(UDC_EPCTL_CNAK); in udc_ep_enable()
427 writel(tmp, &ep->regs->ctl); in udc_ep_enable()
431 tmp = desc->bEndpointAddress; in udc_ep_enable()
441 u32 tmp; in ep_init() local
450 tmp = readl(&ep->regs->ctl); in ep_init()
451 tmp |= AMD_BIT(UDC_EPCTL_SNAK); in ep_init()
452 writel(tmp, &ep->regs->ctl); in ep_init()
456 tmp = readl(®s->ep_irqmsk); in ep_init()
457 tmp |= AMD_BIT(ep->num); in ep_init()
458 writel(tmp, ®s->ep_irqmsk); in ep_init()
462 tmp = readl(&ep->regs->ctl); in ep_init()
463 tmp &= AMD_UNMASK_BIT(UDC_EPCTL_P); in ep_init()
464 writel(tmp, &ep->regs->ctl); in ep_init()
466 tmp = readl(&ep->regs->sts); in ep_init()
467 tmp |= AMD_BIT(UDC_EPSTS_IN); in ep_init()
468 writel(tmp, &ep->regs->sts); in ep_init()
471 tmp = readl(&ep->regs->ctl); in ep_init()
472 tmp |= AMD_BIT(UDC_EPCTL_F); in ep_init()
473 writel(tmp, &ep->regs->ctl); in ep_init()
667 u32 tmp; in udc_rxfifo_read_bytes() local
677 tmp = readl(dev->rxfifo); in udc_rxfifo_read_bytes()
679 *(buf + (i<<2) + j) = (u8)(tmp & UDC_BYTE_MASK); in udc_rxfifo_read_bytes()
680 tmp = tmp >> UDC_BITS_PER_BYTE; in udc_rxfifo_read_bytes()
729 u32 tmp; in prep_dma() local
802 tmp = readl(&ep->regs->ctl); in prep_dma()
803 tmp |= AMD_BIT(UDC_EPCTL_CNAK); in prep_dma()
804 writel(tmp, &ep->regs->ctl); in prep_dma()
1033 u32 tmp; in udc_set_rde() local
1042 tmp = readl(&dev->regs->ctl); in udc_set_rde()
1043 tmp |= AMD_BIT(UDC_DEVCTL_RDE); in udc_set_rde()
1044 writel(tmp, &dev->regs->ctl); in udc_set_rde()
1057 u32 tmp; in udc_queue() local
1105 tmp = readl(&dev->regs->ctl); in udc_queue()
1106 tmp |= AMD_BIT(UDC_DEVCTL_CSR_DONE); in udc_queue()
1107 writel(tmp, &dev->regs->ctl); in udc_queue()
1113 tmp = readl(&dev->ep[UDC_EP0IN_IX].regs->ctl); in udc_queue()
1114 tmp |= AMD_BIT(UDC_EPCTL_CNAK); in udc_queue()
1115 writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->ctl); in udc_queue()
1144 tmp = readl(&dev->regs->ctl); in udc_queue()
1145 tmp &= AMD_UNMASK_BIT(UDC_DEVCTL_RDE); in udc_queue()
1146 writel(tmp, &dev->regs->ctl); in udc_queue()
1165 tmp = readl(&ep->regs->ctl); in udc_queue()
1166 tmp |= AMD_BIT(UDC_EPCTL_CNAK); in udc_queue()
1167 writel(tmp, &ep->regs->ctl); in udc_queue()
1174 tmp = readl(&dev->regs->ep_irqmsk); in udc_queue()
1175 tmp &= AMD_UNMASK_BIT(ep->num); in udc_queue()
1176 writel(tmp, &dev->regs->ep_irqmsk); in udc_queue()
1180 tmp = readl(&dev->regs->ep_irqmsk); in udc_queue()
1181 tmp &= AMD_UNMASK_BIT(ep->num); in udc_queue()
1182 writel(tmp, &dev->regs->ep_irqmsk); in udc_queue()
1273 u32 tmp; in udc_dequeue() local
1276 tmp = readl(&udc->regs->ctl); in udc_dequeue()
1277 writel(tmp & AMD_UNMASK_BIT(UDC_DEVCTL_RDE), in udc_dequeue()
1292 writel(tmp, &udc->regs->ctl); in udc_dequeue()
1308 u32 tmp; in udc_set_halt() local
1333 tmp = readl(&ep->regs->ctl); in udc_set_halt()
1334 tmp |= AMD_BIT(UDC_EPCTL_S); in udc_set_halt()
1335 writel(tmp, &ep->regs->ctl); in udc_set_halt()
1352 tmp = readl(&ep->regs->ctl); in udc_set_halt()
1354 tmp = tmp & AMD_CLEAR_BIT(UDC_EPCTL_S); in udc_set_halt()
1356 tmp |= AMD_BIT(UDC_EPCTL_CNAK); in udc_set_halt()
1357 writel(tmp, &ep->regs->ctl); in udc_set_halt()
1437 u32 tmp; in startup_registers() local
1451 tmp = readl(&dev->regs->cfg); in startup_registers()
1453 tmp = AMD_ADDBITS(tmp, UDC_DEVCFG_SPD_FS, UDC_DEVCFG_SPD); in startup_registers()
1455 tmp = AMD_ADDBITS(tmp, UDC_DEVCFG_SPD_HS, UDC_DEVCFG_SPD); in startup_registers()
1456 writel(tmp, &dev->regs->cfg); in startup_registers()
1464 u32 tmp; in udc_basic_init() local
1479 tmp = readl(&dev->regs->ctl); in udc_basic_init()
1480 tmp &= AMD_UNMASK_BIT(UDC_DEVCTL_RDE); in udc_basic_init()
1481 tmp &= AMD_UNMASK_BIT(UDC_DEVCTL_TDE); in udc_basic_init()
1482 writel(tmp, &dev->regs->ctl); in udc_basic_init()
1485 tmp = readl(&dev->regs->cfg); in udc_basic_init()
1486 tmp |= AMD_BIT(UDC_DEVCFG_CSR_PRG); in udc_basic_init()
1488 tmp |= AMD_BIT(UDC_DEVCFG_SP); in udc_basic_init()
1490 tmp |= AMD_BIT(UDC_DEVCFG_RWKP); in udc_basic_init()
1491 writel(tmp, &dev->regs->cfg); in udc_basic_init()
1503 u32 tmp; in udc_setup_endpoints() local
1509 tmp = readl(&dev->regs->sts); in udc_setup_endpoints()
1510 tmp = AMD_GETBITS(tmp, UDC_DEVSTS_ENUM_SPEED); in udc_setup_endpoints()
1511 if (tmp == UDC_DEVSTS_ENUM_SPEED_HIGH) in udc_setup_endpoints()
1513 else if (tmp == UDC_DEVSTS_ENUM_SPEED_FULL) in udc_setup_endpoints()
1517 for (tmp = 0; tmp < UDC_EP_NUM; tmp++) { in udc_setup_endpoints()
1518 ep = &dev->ep[tmp]; in udc_setup_endpoints()
1520 ep->ep.name = ep_string[tmp]; in udc_setup_endpoints()
1521 ep->num = tmp; in udc_setup_endpoints()
1526 if (tmp < UDC_EPIN_NUM) { in udc_setup_endpoints()
1534 ep->regs = &dev->ep_regs[tmp]; in udc_setup_endpoints()
1552 if (tmp != UDC_EP0IN_IX && tmp != UDC_EP0OUT_IX in udc_setup_endpoints()
1553 && tmp > UDC_EPIN_NUM) { in udc_setup_endpoints()
1555 reg = readl(&dev->ep[tmp].regs->ctl); in udc_setup_endpoints()
1557 writel(reg, &dev->ep[tmp].regs->ctl); in udc_setup_endpoints()
1558 dev->ep[tmp].naking = 1; in udc_setup_endpoints()
1631 u32 tmp; in udc_tasklet_disconnect() local
1642 for (tmp = 0; tmp < UDC_EP_NUM; tmp++) in udc_tasklet_disconnect()
1643 empty_req_queue(&dev->ep[tmp]); in udc_tasklet_disconnect()
1662 tmp = readl(&dev->regs->cfg); in udc_tasklet_disconnect()
1663 tmp = AMD_ADDBITS(tmp, UDC_DEVCFG_SPD_FS, UDC_DEVCFG_SPD); in udc_tasklet_disconnect()
1664 writel(tmp, &dev->regs->cfg); in udc_tasklet_disconnect()
1695 u32 tmp; in udc_timer_function() local
1706 tmp = readl(&udc->regs->ctl); in udc_timer_function()
1707 tmp |= AMD_BIT(UDC_DEVCTL_RDE); in udc_timer_function()
1708 writel(tmp, &udc->regs->ctl); in udc_timer_function()
1745 u32 tmp; in udc_handle_halt_state() local
1748 tmp = readl(&ep->regs->ctl); in udc_handle_halt_state()
1750 if (!(tmp & AMD_BIT(UDC_EPCTL_S))) { in udc_handle_halt_state()
1764 tmp |= AMD_BIT(UDC_EPCTL_CNAK); in udc_handle_halt_state()
1765 writel(tmp, &ep->regs->ctl); in udc_handle_halt_state()
1809 u32 tmp; in activate_control_endpoints() local
1814 tmp = readl(&dev->ep[UDC_EP0IN_IX].regs->ctl); in activate_control_endpoints()
1815 tmp |= AMD_BIT(UDC_EPCTL_F); in activate_control_endpoints()
1816 writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->ctl); in activate_control_endpoints()
1823 tmp = readl(&dev->ep[UDC_EP0IN_IX].regs->bufin_framenum); in activate_control_endpoints()
1825 tmp = AMD_ADDBITS(tmp, UDC_FS_EPIN0_BUFF_SIZE, in activate_control_endpoints()
1828 tmp = AMD_ADDBITS(tmp, UDC_EPIN0_BUFF_SIZE, in activate_control_endpoints()
1830 writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->bufin_framenum); in activate_control_endpoints()
1833 tmp = readl(&dev->ep[UDC_EP0IN_IX].regs->bufout_maxpkt); in activate_control_endpoints()
1835 tmp = AMD_ADDBITS(tmp, UDC_FS_EP0IN_MAX_PKT_SIZE, in activate_control_endpoints()
1838 tmp = AMD_ADDBITS(tmp, UDC_EP0IN_MAX_PKT_SIZE, in activate_control_endpoints()
1840 writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->bufout_maxpkt); in activate_control_endpoints()
1843 tmp = readl(&dev->ep[UDC_EP0OUT_IX].regs->bufout_maxpkt); in activate_control_endpoints()
1845 tmp = AMD_ADDBITS(tmp, UDC_FS_EP0OUT_MAX_PKT_SIZE, in activate_control_endpoints()
1848 tmp = AMD_ADDBITS(tmp, UDC_EP0OUT_MAX_PKT_SIZE, in activate_control_endpoints()
1850 writel(tmp, &dev->ep[UDC_EP0OUT_IX].regs->bufout_maxpkt); in activate_control_endpoints()
1853 tmp = readl(&dev->csr->ne[0]); in activate_control_endpoints()
1855 tmp = AMD_ADDBITS(tmp, UDC_FS_EP0OUT_MAX_PKT_SIZE, in activate_control_endpoints()
1858 tmp = AMD_ADDBITS(tmp, UDC_EP0OUT_MAX_PKT_SIZE, in activate_control_endpoints()
1860 writel(tmp, &dev->csr->ne[0]); in activate_control_endpoints()
1879 tmp = readl(&dev->regs->ctl); in activate_control_endpoints()
1880 tmp |= AMD_BIT(UDC_DEVCTL_MODE) in activate_control_endpoints()
1884 tmp |= AMD_BIT(UDC_DEVCTL_BF); in activate_control_endpoints()
1886 tmp |= AMD_BIT(UDC_DEVCTL_DU); in activate_control_endpoints()
1887 writel(tmp, &dev->regs->ctl); in activate_control_endpoints()
1891 tmp = readl(&dev->ep[UDC_EP0IN_IX].regs->ctl); in activate_control_endpoints()
1892 tmp |= AMD_BIT(UDC_EPCTL_CNAK); in activate_control_endpoints()
1893 writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->ctl); in activate_control_endpoints()
1898 tmp = readl(&dev->ep[UDC_EP0OUT_IX].regs->ctl); in activate_control_endpoints()
1899 tmp |= AMD_BIT(UDC_EPCTL_CNAK); in activate_control_endpoints()
1900 writel(tmp, &dev->ep[UDC_EP0OUT_IX].regs->ctl); in activate_control_endpoints()
1922 u32 tmp; in amd5536_udc_start() local
1937 tmp = readl(&dev->regs->ctl); in amd5536_udc_start()
1938 tmp = tmp & AMD_CLEAR_BIT(UDC_DEVCTL_SD); in amd5536_udc_start()
1939 writel(tmp, &dev->regs->ctl); in amd5536_udc_start()
1952 int tmp; in shutdown() local
1957 for (tmp = 0; tmp < UDC_EP_NUM; tmp++) in shutdown()
1958 empty_req_queue(&dev->ep[tmp]); in shutdown()
1968 u32 tmp; in amd5536_udc_stop() local
1978 tmp = readl(&dev->regs->ctl); in amd5536_udc_stop()
1979 tmp |= AMD_BIT(UDC_DEVCTL_SD); in amd5536_udc_stop()
1980 writel(tmp, &dev->regs->ctl); in amd5536_udc_stop()
1988 u32 tmp; in udc_process_cnak_queue() local
1993 for (tmp = 0; tmp < UDC_EPIN_NUM_USED; tmp++) { in udc_process_cnak_queue()
1994 if (cnak_pending & (1 << tmp)) { in udc_process_cnak_queue()
1995 DBG(dev, "CNAK pending for ep%d\n", tmp); in udc_process_cnak_queue()
1997 reg = readl(&dev->ep[tmp].regs->ctl); in udc_process_cnak_queue()
1999 writel(reg, &dev->ep[tmp].regs->ctl); in udc_process_cnak_queue()
2000 dev->ep[tmp].naking = 0; in udc_process_cnak_queue()
2001 UDC_QUEUE_CNAK(&dev->ep[tmp], dev->ep[tmp].num); in udc_process_cnak_queue()
2048 u32 tmp; in udc_data_out_isr() local
2058 tmp = readl(&ep->regs->sts); in udc_data_out_isr()
2061 if (tmp & AMD_BIT(UDC_EPSTS_BNA)) { in udc_data_out_isr()
2065 writel(tmp | AMD_BIT(UDC_EPSTS_BNA), &ep->regs->sts); in udc_data_out_isr()
2075 if (tmp & AMD_BIT(UDC_EPSTS_HE)) { in udc_data_out_isr()
2079 writel(tmp | AMD_BIT(UDC_EPSTS_HE), &ep->regs->sts); in udc_data_out_isr()
2166 tmp = req->req.length - req->req.actual; in udc_data_out_isr()
2167 if (count > tmp) { in udc_data_out_isr()
2168 if ((tmp % ep->ep.maxpacket) != 0) { in udc_data_out_isr()
2170 ep->ep.name, count, tmp); in udc_data_out_isr()
2173 count = tmp; in udc_data_out_isr()
2262 u32 tmp; in udc_data_in_isr() local
2331 tmp = readl(&dev->regs->ep_irqmsk); in udc_data_in_isr()
2332 tmp |= AMD_BIT(ep->num); in udc_data_in_isr()
2333 writel(tmp, &dev->regs->ep_irqmsk); in udc_data_in_isr()
2394 tmp = readl(&ep->regs->ctl); in udc_data_in_isr()
2395 tmp |= AMD_BIT(UDC_EPCTL_P); in udc_data_in_isr()
2396 writel(tmp, &ep->regs->ctl); in udc_data_in_isr()
2402 tmp = readl( in udc_data_in_isr()
2404 tmp |= AMD_BIT(ep->num); in udc_data_in_isr()
2405 writel(tmp, in udc_data_in_isr()
2423 u32 tmp; in udc_control_out_isr() local
2435 tmp = readl(&dev->ep[UDC_EP0OUT_IX].regs->sts); in udc_control_out_isr()
2437 if (tmp & AMD_BIT(UDC_EPSTS_BNA)) { in udc_control_out_isr()
2447 tmp = AMD_GETBITS(tmp, UDC_EPSTS_OUT); in udc_control_out_isr()
2448 VDBG(dev, "data_typ = %x\n", tmp); in udc_control_out_isr()
2451 if (tmp == UDC_EPSTS_OUT_SETUP) { in udc_control_out_isr()
2458 tmp = readl(&dev->ep[UDC_EP0IN_IX].regs->ctl); in udc_control_out_isr()
2459 tmp |= AMD_BIT(UDC_EPCTL_SNAK); in udc_control_out_isr()
2460 writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->ctl); in udc_control_out_isr()
2540 tmp = readl(&dev->ep[UDC_EP0IN_IX].regs->ctl); in udc_control_out_isr()
2545 tmp |= AMD_BIT(UDC_EPCTL_CNAK); in udc_control_out_isr()
2546 writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->ctl); in udc_control_out_isr()
2552 tmp |= AMD_BIT(UDC_EPCTL_S); in udc_control_out_isr()
2553 writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->ctl); in udc_control_out_isr()
2560 tmp = readl(&dev->ep[UDC_EP0OUT_IX].regs->ctl); in udc_control_out_isr()
2561 tmp |= AMD_BIT(UDC_EPCTL_CNAK); in udc_control_out_isr()
2562 writel(tmp, &dev->ep[UDC_EP0OUT_IX].regs->ctl); in udc_control_out_isr()
2574 } else if (tmp == UDC_EPSTS_OUT_DATA) { in udc_control_out_isr()
2637 u32 tmp; in udc_control_in_isr() local
2647 tmp = readl(&dev->ep[UDC_EP0IN_IX].regs->sts); in udc_control_in_isr()
2649 if (tmp & AMD_BIT(UDC_EPSTS_TDC)) { in udc_control_in_isr()
2658 } else if (tmp & AMD_BIT(UDC_EPSTS_IN)) { in udc_control_in_isr()
2669 tmp = readl(&ep->regs->ctl); in udc_control_in_isr()
2670 tmp |= AMD_BIT(UDC_EPCTL_S); in udc_control_in_isr()
2671 writel(tmp, &ep->regs->ctl); in udc_control_in_isr()
2689 tmp = in udc_control_in_isr()
2691 tmp |= AMD_BIT(UDC_EPCTL_P); in udc_control_in_isr()
2692 writel(tmp, in udc_control_in_isr()
2739 u32 tmp; in udc_dev_isr() local
2750 tmp = readl(&dev->regs->sts); in udc_dev_isr()
2751 cfg = AMD_GETBITS(tmp, UDC_DEVSTS_CFG); in udc_dev_isr()
2776 tmp = readl(&dev->csr->ne[udc_csr_epix]); in udc_dev_isr()
2778 tmp = AMD_ADDBITS(tmp, ep->dev->cur_config, in udc_dev_isr()
2781 writel(tmp, &dev->csr->ne[udc_csr_epix]); in udc_dev_isr()
2785 tmp = readl(&ep->regs->ctl); in udc_dev_isr()
2786 tmp = tmp & AMD_CLEAR_BIT(UDC_EPCTL_S); in udc_dev_isr()
2787 writel(tmp, &ep->regs->ctl); in udc_dev_isr()
2791 tmp = dev->driver->setup(&dev->gadget, &setup_data.request); in udc_dev_isr()
2800 tmp = readl(&dev->regs->sts); in udc_dev_isr()
2801 dev->cur_alt = AMD_GETBITS(tmp, UDC_DEVSTS_ALT); in udc_dev_isr()
2802 dev->cur_intf = AMD_GETBITS(tmp, UDC_DEVSTS_INTF); in udc_dev_isr()
2831 tmp = readl(&dev->csr->ne[udc_csr_epix]); in udc_dev_isr()
2833 tmp = AMD_ADDBITS(tmp, ep->dev->cur_intf, in udc_dev_isr()
2837 tmp = AMD_ADDBITS(tmp, ep->dev->cur_alt, in udc_dev_isr()
2840 writel(tmp, &dev->csr->ne[udc_csr_epix]); in udc_dev_isr()
2844 tmp = readl(&ep->regs->ctl); in udc_dev_isr()
2845 tmp = tmp & AMD_CLEAR_BIT(UDC_EPCTL_S); in udc_dev_isr()
2846 writel(tmp, &ep->regs->ctl); in udc_dev_isr()
2851 tmp = dev->driver->setup(&dev->gadget, &setup_data.request); in udc_dev_isr()
2882 tmp = readl(&dev->regs->sts); in udc_dev_isr()
2883 if (!(tmp & AMD_BIT(UDC_DEVSTS_RXFIFO_EMPTY)) in udc_dev_isr()
2895 tmp = readl(&dev->regs->cfg); in udc_dev_isr()
2896 writel(tmp | AMD_BIT(UDC_DEVCFG_DMARST), &dev->regs->cfg); in udc_dev_isr()
2897 writel(tmp, &dev->regs->cfg); in udc_dev_isr()
2906 tmp = readl(&dev->regs->irqmsk); in udc_dev_isr()
2907 tmp &= AMD_UNMASK_BIT(UDC_DEVINT_US); in udc_dev_isr()
2908 writel(tmp, &dev->regs->irqmsk); in udc_dev_isr()
2947 tmp = readl(&dev->regs->sts); in udc_dev_isr()
2948 if (!(tmp & AMD_BIT(UDC_DEVSTS_SESSVLD))) { in udc_dev_isr()
2950 tmp = readl(&dev->regs->irqmsk); in udc_dev_isr()
2951 tmp |= AMD_BIT(UDC_DEVINT_US); in udc_dev_isr()
2952 writel(tmp, &dev->regs->irqmsk); in udc_dev_isr()
3257 char tmp[128]; in udc_probe() local
3277 snprintf(tmp, sizeof tmp, "%d", dev->irq); in udc_probe()
3280 tmp, dev->phys_addr, dev->chiprev, in udc_probe()
3282 strcpy(tmp, UDC_DRIVER_VERSION_STRING); in udc_probe()
3289 "driver version: %s(for Geode5536 B1)\n", tmp); in udc_probe()
3324 u32 tmp; in udc_remote_wakeup() local
3330 tmp = readl(&dev->regs->ctl); in udc_remote_wakeup()
3331 tmp |= AMD_BIT(UDC_DEVCTL_RES); in udc_remote_wakeup()
3332 writel(tmp, &dev->regs->ctl); in udc_remote_wakeup()
3333 tmp &= AMD_CLEAR_BIT(UDC_DEVCTL_RES); in udc_remote_wakeup()
3334 writel(tmp, &dev->regs->ctl); in udc_remote_wakeup()