33 	xhci_dbg(xhci, "// xHCI capability registers at %p:\n",  in xhci_dbg_regs()
36 	xhci_dbg(xhci, "// @%p = 0x%x (CAPLENGTH AND HCIVERSION)\n",  in xhci_dbg_regs()
38 	xhci_dbg(xhci, "//   CAPLENGTH: 0x%x\n",  in xhci_dbg_regs()
41 	xhci_dbg(xhci, "//   HCIVERSION: 0x%x\n",  in xhci_dbg_regs()
45 	xhci_dbg(xhci, "// xHCI operational registers at %p:\n", xhci->op_regs);  in xhci_dbg_regs()
48 	xhci_dbg(xhci, "// @%p = 0x%x RTSOFF\n",  in xhci_dbg_regs()
51 	xhci_dbg(xhci, "// xHCI runtime registers at %p:\n", xhci->run_regs);  in xhci_dbg_regs()
54 	xhci_dbg(xhci, "// @%p = 0x%x DBOFF\n", &xhci->cap_regs->db_off, temp);  in xhci_dbg_regs()
55 	xhci_dbg(xhci, "// Doorbell array at %p:\n", xhci->dba);  in xhci_dbg_regs()
62 	xhci_dbg(xhci, "xHCI capability registers at %p:\n", xhci->cap_regs);  in xhci_print_cap_regs()
65 	xhci_dbg(xhci, "CAPLENGTH AND HCIVERSION 0x%x:\n",  in xhci_print_cap_regs()
67 	xhci_dbg(xhci, "CAPLENGTH: 0x%x\n",  in xhci_print_cap_regs()
69 	xhci_dbg(xhci, "HCIVERSION: 0x%x\n",  in xhci_print_cap_regs()
73 	xhci_dbg(xhci, "HCSPARAMS 1: 0x%x\n",  in xhci_print_cap_regs()
75 	xhci_dbg(xhci, "  Max device slots: %u\n",  in xhci_print_cap_regs()
77 	xhci_dbg(xhci, "  Max interrupters: %u\n",  in xhci_print_cap_regs()
79 	xhci_dbg(xhci, "  Max ports: %u\n",  in xhci_print_cap_regs()
83 	xhci_dbg(xhci, "HCSPARAMS 2: 0x%x\n",  in xhci_print_cap_regs()
85 	xhci_dbg(xhci, "  Isoc scheduling threshold: %u\n",  in xhci_print_cap_regs()
87 	xhci_dbg(xhci, "  Maximum allowed segments in event ring: %u\n",  in xhci_print_cap_regs()
91 	xhci_dbg(xhci, "HCSPARAMS 3 0x%x:\n",  in xhci_print_cap_regs()
93 	xhci_dbg(xhci, "  Worst case U1 device exit latency: %u\n",  in xhci_print_cap_regs()
95 	xhci_dbg(xhci, "  Worst case U2 device exit latency: %u\n",  in xhci_print_cap_regs()
99 	xhci_dbg(xhci, "HCC PARAMS 0x%x:\n", (unsigned int) temp);  in xhci_print_cap_regs()
100 	xhci_dbg(xhci, "  HC generates %s bit addresses\n",  in xhci_print_cap_regs()
103 	xhci_dbg(xhci, "  FIXME: more HCCPARAMS debugging\n");  in xhci_print_cap_regs()
106 	xhci_dbg(xhci, "RTSOFF 0x%x:\n", temp & RTSOFF_MASK);  in xhci_print_cap_regs()
114 	xhci_dbg(xhci, "USBCMD 0x%x:\n", temp);  in xhci_print_command_reg()
115 	xhci_dbg(xhci, "  HC is %s\n",  in xhci_print_command_reg()
117 	xhci_dbg(xhci, "  HC has %sfinished hard reset\n",  in xhci_print_command_reg()
119 	xhci_dbg(xhci, "  Event Interrupts %s\n",  in xhci_print_command_reg()
121 	xhci_dbg(xhci, "  Host System Error Interrupts %s\n",  in xhci_print_command_reg()
123 	xhci_dbg(xhci, "  HC has %sfinished light reset\n",  in xhci_print_command_reg()
132 	xhci_dbg(xhci, "USBSTS 0x%x:\n", temp);  in xhci_print_status()
133 	xhci_dbg(xhci, "  Event ring is %sempty\n",  in xhci_print_status()
135 	xhci_dbg(xhci, "  %sHost System Error\n",  in xhci_print_status()
137 	xhci_dbg(xhci, "  HC is %s\n",  in xhci_print_status()
143 	xhci_dbg(xhci, "xHCI operational registers at %p:\n", xhci->op_regs);  in xhci_print_op_regs()
164 			xhci_dbg(xhci, "%p port %s reg = 0x%x\n",  in xhci_print_ports()
184 	xhci_dbg(xhci, "  %p: ir_set[%i]\n", ir_set, set_num);  in xhci_print_ir_set()
186 	xhci_dbg(xhci, "  %p: ir_set.pending = 0x%x\n", addr,  in xhci_print_ir_set()
191 	xhci_dbg(xhci, "  %p: ir_set.control = 0x%x\n", addr,  in xhci_print_ir_set()
196 	xhci_dbg(xhci, "  %p: ir_set.erst_size = 0x%x\n", addr,  in xhci_print_ir_set()
202 		xhci_dbg(xhci, "  WARN: %p: ir_set.rsvd = 0x%x\n",  in xhci_print_ir_set()
207 	xhci_dbg(xhci, "  %p: ir_set.erst_base = @%08llx\n",  in xhci_print_ir_set()
212 	xhci_dbg(xhci, "  %p: ir_set.erst_dequeue = @%08llx\n",  in xhci_print_ir_set()
221 	xhci_dbg(xhci, "xHCI runtime registers at %p:\n", xhci->run_regs);  in xhci_print_run_regs()
223 	xhci_dbg(xhci, "  %p: Microframe index = 0x%x\n",  in xhci_print_run_regs()
229 			xhci_dbg(xhci, "  WARN: %p: Rsvd[%i] = 0x%x\n",  in xhci_print_run_regs()
246 		xhci_dbg(xhci, "Offset 0x%x = 0x%x\n",  in xhci_print_trb_offsets()
260 		xhci_dbg(xhci, "Link TRB:\n");  in xhci_debug_trb()
264 		xhci_dbg(xhci, "Next ring segment DMA address = 0x%llx\n", address);  in xhci_debug_trb()
266 		xhci_dbg(xhci, "Interrupter target = 0x%x\n",  in xhci_debug_trb()
268 		xhci_dbg(xhci, "Cycle bit = %u\n",  in xhci_debug_trb()
270 		xhci_dbg(xhci, "Toggle cycle bit = %u\n",  in xhci_debug_trb()
272 		xhci_dbg(xhci, "No Snoop bit = %u\n",  in xhci_debug_trb()
281 		xhci_dbg(xhci, "DMA address or buffer contents= %llu\n", address);  in xhci_debug_trb()
285 		xhci_dbg(xhci, "Command TRB pointer = %llu\n", address);  in xhci_debug_trb()
286 		xhci_dbg(xhci, "Completion status = %u\n",  in xhci_debug_trb()
288 		xhci_dbg(xhci, "Flags = 0x%x\n",  in xhci_debug_trb()
292 		xhci_dbg(xhci, "Unknown TRB with TRB type ID %u\n",  in xhci_debug_trb()
320 		xhci_dbg(xhci, "@%016llx %08x %08x %08x %08x\n", addr,  in xhci_debug_segment()
331 	xhci_dbg(xhci, "Ring deq = %p (virt), 0x%llx (dma)\n",  in xhci_dbg_ring_ptrs()
335 	xhci_dbg(xhci, "Ring deq updated %u times\n",  in xhci_dbg_ring_ptrs()
337 	xhci_dbg(xhci, "Ring enq = %p (virt), 0x%llx (dma)\n",  in xhci_dbg_ring_ptrs()
341 	xhci_dbg(xhci, "Ring enq updated %u times\n",  in xhci_dbg_ring_ptrs()
362 		xhci_dbg(xhci, "  Ring has not been updated\n");  in xhci_debug_ring()
379 			xhci_dbg(xhci, "Dev %d endpoint %d stream ID %d:\n",  in xhci_dbg_ep_rings()
387 		xhci_dbg(xhci, "Dev %d endpoint ring %d:\n",  in xhci_dbg_ep_rings()
401 		xhci_dbg(xhci, "@%016llx %08x %08x %08x %08x\n",  in xhci_dbg_erst()
416 	xhci_dbg(xhci, "// xHC command ring deq ptr low bits + flags = @%08x\n",  in xhci_dbg_cmd_ptrs()
418 	xhci_dbg(xhci, "// xHC command ring deq ptr high bits = @%08x\n",  in xhci_dbg_cmd_ptrs()
427 		xhci_dbg(xhci, "@%p (virt) @%08llx "  in dbg_rsvd64()
465 	xhci_dbg(xhci, "Slot Context:\n");  in xhci_dbg_slot_ctx()
466 	xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - dev_info\n",  in xhci_dbg_slot_ctx()
470 	xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - dev_info2\n",  in xhci_dbg_slot_ctx()
474 	xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - tt_info\n",  in xhci_dbg_slot_ctx()
478 	xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - dev_state\n",  in xhci_dbg_slot_ctx()
483 		xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - rsvd[%d]\n",  in xhci_dbg_slot_ctx()
511 		xhci_dbg(xhci, "%s Endpoint %02d Context (ep_index %02d):\n",  in xhci_dbg_ep_ctx()
514 		xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - ep_info\n",  in xhci_dbg_ep_ctx()
518 		xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - ep_info2\n",  in xhci_dbg_ep_ctx()
522 		xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08llx - deq\n",  in xhci_dbg_ep_ctx()
526 		xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - tx_info\n",  in xhci_dbg_ep_ctx()
531 			xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - rsvd[%d]\n",  in xhci_dbg_ep_ctx()
561 		xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - drop flags\n",  in xhci_dbg_ctx()
565 		xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - add flags\n",  in xhci_dbg_ctx()
570 			xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - rsvd2[%d]\n",  in xhci_dbg_ctx()
593 	xhci_dbg(xhci, "%pV\n", &vaf);  in xhci_dbg_trace()