Lines Matching refs:temp
56 u16 temp; in xhci_common_hub_descriptor() local
62 temp = 0; in xhci_common_hub_descriptor()
65 temp |= HUB_CHAR_INDV_PORT_LPSM; in xhci_common_hub_descriptor()
67 temp |= HUB_CHAR_NO_LPSM; in xhci_common_hub_descriptor()
70 temp |= HUB_CHAR_INDV_PORT_OCPM; in xhci_common_hub_descriptor()
73 desc->wHubCharacteristics = cpu_to_le16(temp); in xhci_common_hub_descriptor()
81 u16 temp; in xhci_usb2_hub_descriptor() local
90 temp = 1 + (ports / 8); in xhci_usb2_hub_descriptor()
91 desc->bDescLength = USB_DT_HUB_NONVAR_SIZE + 2 * temp; in xhci_usb2_hub_descriptor()
424 u32 temp; in xhci_set_link_state() local
426 temp = readl(port_array[port_id]); in xhci_set_link_state()
427 temp = xhci_port_state_to_neutral(temp); in xhci_set_link_state()
428 temp &= ~PORT_PLS_MASK; in xhci_set_link_state()
429 temp |= PORT_LINK_STROBE | link_state; in xhci_set_link_state()
430 writel(temp, port_array[port_id]); in xhci_set_link_state()
436 u32 temp; in xhci_set_remote_wake_mask() local
438 temp = readl(port_array[port_id]); in xhci_set_remote_wake_mask()
439 temp = xhci_port_state_to_neutral(temp); in xhci_set_remote_wake_mask()
442 temp |= PORT_WKCONN_E; in xhci_set_remote_wake_mask()
444 temp &= ~PORT_WKCONN_E; in xhci_set_remote_wake_mask()
447 temp |= PORT_WKDISC_E; in xhci_set_remote_wake_mask()
449 temp &= ~PORT_WKDISC_E; in xhci_set_remote_wake_mask()
452 temp |= PORT_WKOC_E; in xhci_set_remote_wake_mask()
454 temp &= ~PORT_WKOC_E; in xhci_set_remote_wake_mask()
456 writel(temp, port_array[port_id]); in xhci_set_remote_wake_mask()
463 u32 temp; in xhci_test_and_clear_bit() local
465 temp = readl(port_array[port_id]); in xhci_test_and_clear_bit()
466 if (temp & port_bit) { in xhci_test_and_clear_bit()
467 temp = xhci_port_state_to_neutral(temp); in xhci_test_and_clear_bit()
468 temp |= port_bit; in xhci_test_and_clear_bit()
469 writel(temp, port_array[port_id]); in xhci_test_and_clear_bit()
714 u32 temp, status; in xhci_hub_control() local
758 temp = readl(&xhci->cap_regs->hcs_params3); in xhci_hub_control()
759 buf[12] = HCS_U1_LATENCY(temp); in xhci_hub_control()
760 put_unaligned_le16(HCS_U2_LATENCY(temp), &buf[13]); in xhci_hub_control()
764 temp = readl(&xhci->cap_regs->hcc_params); in xhci_hub_control()
765 if (HCC_LTC(temp)) in xhci_hub_control()
774 temp = readl(port_array[wIndex]); in xhci_hub_control()
775 if (temp == 0xffffffff) { in xhci_hub_control()
780 wIndex, temp, flags); in xhci_hub_control()
785 wIndex, temp); in xhci_hub_control()
801 temp = readl(port_array[wIndex]); in xhci_hub_control()
802 if (temp == 0xffffffff) { in xhci_hub_control()
806 temp = xhci_port_state_to_neutral(temp); in xhci_hub_control()
810 temp = readl(port_array[wIndex]); in xhci_hub_control()
811 if ((temp & PORT_PLS_MASK) != XDEV_U0) { in xhci_hub_control()
823 temp = readl(port_array[wIndex]); in xhci_hub_control()
824 if ((temp & PORT_PE) == 0 || (temp & PORT_RESET) in xhci_hub_control()
825 || (temp & PORT_PLS_MASK) >= XDEV_U3) { in xhci_hub_control()
848 temp = readl(port_array[wIndex]); in xhci_hub_control()
852 temp = readl(port_array[wIndex]); in xhci_hub_control()
857 temp = xhci_port_state_to_neutral(temp); in xhci_hub_control()
862 temp |= PORT_CSC | PORT_PEC | PORT_WRC | in xhci_hub_control()
865 writel(temp | PORT_PE, port_array[wIndex]); in xhci_hub_control()
866 temp = readl(port_array[wIndex]); in xhci_hub_control()
875 temp = readl(port_array[wIndex]); in xhci_hub_control()
883 if ((temp & PORT_PE) == 0 || in xhci_hub_control()
909 temp = readl(port_array[wIndex]); in xhci_hub_control()
920 writel(temp | PORT_POWER, port_array[wIndex]); in xhci_hub_control()
922 temp = readl(port_array[wIndex]); in xhci_hub_control()
923 xhci_dbg(xhci, "set port power, actual port %d status = 0x%x\n", wIndex, temp); in xhci_hub_control()
926 temp = usb_acpi_power_manageable(hcd->self.root_hub, in xhci_hub_control()
928 if (temp) in xhci_hub_control()
934 temp = (temp | PORT_RESET); in xhci_hub_control()
935 writel(temp, port_array[wIndex]); in xhci_hub_control()
937 temp = readl(port_array[wIndex]); in xhci_hub_control()
938 xhci_dbg(xhci, "set port reset, actual port %d status = 0x%x\n", wIndex, temp); in xhci_hub_control()
943 temp = readl(port_array[wIndex]); in xhci_hub_control()
946 wIndex, temp); in xhci_hub_control()
949 temp |= PORT_WR; in xhci_hub_control()
950 writel(temp, port_array[wIndex]); in xhci_hub_control()
952 temp = readl(port_array[wIndex]); in xhci_hub_control()
957 temp = readl(port_array[wIndex] + PORTPMSC); in xhci_hub_control()
958 temp &= ~PORT_U1_TIMEOUT_MASK; in xhci_hub_control()
959 temp |= PORT_U1_TIMEOUT(timeout); in xhci_hub_control()
960 writel(temp, port_array[wIndex] + PORTPMSC); in xhci_hub_control()
965 temp = readl(port_array[wIndex] + PORTPMSC); in xhci_hub_control()
966 temp &= ~PORT_U2_TIMEOUT_MASK; in xhci_hub_control()
967 temp |= PORT_U2_TIMEOUT(timeout); in xhci_hub_control()
968 writel(temp, port_array[wIndex] + PORTPMSC); in xhci_hub_control()
974 temp = readl(port_array[wIndex]); in xhci_hub_control()
980 temp = readl(port_array[wIndex]); in xhci_hub_control()
981 if (temp == 0xffffffff) { in xhci_hub_control()
986 temp = xhci_port_state_to_neutral(temp); in xhci_hub_control()
989 temp = readl(port_array[wIndex]); in xhci_hub_control()
991 xhci_dbg(xhci, "PORTSC %04x\n", temp); in xhci_hub_control()
992 if (temp & PORT_RESET) in xhci_hub_control()
994 if ((temp & PORT_PLS_MASK) == XDEV_U3) { in xhci_hub_control()
995 if ((temp & PORT_PE) == 0) in xhci_hub_control()
1026 port_array[wIndex], temp); in xhci_hub_control()
1030 port_array[wIndex], temp); in xhci_hub_control()
1033 writel(temp & ~PORT_POWER, port_array[wIndex]); in xhci_hub_control()
1036 temp = usb_acpi_power_manageable(hcd->self.root_hub, in xhci_hub_control()
1038 if (temp) in xhci_hub_control()
1067 u32 temp, status; in xhci_hub_status_data() local
1094 temp = readl(port_array[i]); in xhci_hub_status_data()
1095 if (temp == 0xffffffff) { in xhci_hub_status_data()
1099 if ((temp & mask) != 0 || in xhci_hub_status_data()
1106 if ((temp & PORT_RC)) in xhci_hub_status_data()
1195 u32 temp; in xhci_bus_resume() local
1211 temp = readl(&xhci->op_regs->command); in xhci_bus_resume()
1212 temp &= ~CMD_EIE; in xhci_bus_resume()
1213 writel(temp, &xhci->op_regs->command); in xhci_bus_resume()
1219 u32 temp; in xhci_bus_resume() local
1222 temp = readl(port_array[port_index]); in xhci_bus_resume()
1223 if (DEV_SUPERSPEED(temp)) in xhci_bus_resume()
1224 temp &= ~(PORT_RWC_BITS | PORT_CEC | PORT_WAKE_BITS); in xhci_bus_resume()
1226 temp &= ~(PORT_RWC_BITS | PORT_WAKE_BITS); in xhci_bus_resume()
1228 (temp & PORT_PLS_MASK)) { in xhci_bus_resume()
1229 if (DEV_SUPERSPEED(temp)) { in xhci_bus_resume()
1259 writel(temp, port_array[port_index]); in xhci_bus_resume()
1266 temp = readl(&xhci->op_regs->command); in xhci_bus_resume()
1267 temp |= CMD_EIE; in xhci_bus_resume()
1268 writel(temp, &xhci->op_regs->command); in xhci_bus_resume()
1269 temp = readl(&xhci->op_regs->command); in xhci_bus_resume()