90 	halted = readl(&xhci->op_regs->status) & STS_HALT;  in xhci_quiesce()
94 	cmd = readl(&xhci->op_regs->command);  in xhci_quiesce()
96 	writel(cmd, &xhci->op_regs->command);  in xhci_quiesce()
113 	ret = xhci_handshake(&xhci->op_regs->status,  in xhci_halt()
132 	temp = readl(&xhci->op_regs->command);  in xhci_start()
136 	writel(temp, &xhci->op_regs->command);  in xhci_start()
142 	ret = xhci_handshake(&xhci->op_regs->status,  in xhci_start()
168 	state = readl(&xhci->op_regs->status);  in xhci_reset()
175 	command = readl(&xhci->op_regs->command);  in xhci_reset()
177 	writel(command, &xhci->op_regs->command);  in xhci_reset()
189 	ret = xhci_handshake(&xhci->op_regs->command,  in xhci_reset()
200 	ret = xhci_handshake(&xhci->op_regs->status,  in xhci_reset()
642 	temp = readl(&xhci->op_regs->command);  in xhci_run()
646 	writel(temp, &xhci->op_regs->command);  in xhci_run()
730 	temp = readl(&xhci->op_regs->status);  in xhci_stop()
731 	writel(temp & ~STS_EINT, &xhci->op_regs->status);  in xhci_stop()
740 			readl(&xhci->op_regs->status));  in xhci_stop()
771 			readl(&xhci->op_regs->status));  in xhci_shutdown()
781 	xhci->s3.command = readl(&xhci->op_regs->command);  in xhci_save_registers()
782 	xhci->s3.dev_nt = readl(&xhci->op_regs->dev_notification);  in xhci_save_registers()
783 	xhci->s3.dcbaa_ptr = xhci_read_64(xhci, &xhci->op_regs->dcbaa_ptr);  in xhci_save_registers()
784 	xhci->s3.config_reg = readl(&xhci->op_regs->config_reg);  in xhci_save_registers()
794 	writel(xhci->s3.command, &xhci->op_regs->command);  in xhci_restore_registers()
795 	writel(xhci->s3.dev_nt, &xhci->op_regs->dev_notification);  in xhci_restore_registers()
796 	xhci_write_64(xhci, xhci->s3.dcbaa_ptr, &xhci->op_regs->dcbaa_ptr);  in xhci_restore_registers()
797 	writel(xhci->s3.config_reg, &xhci->op_regs->config_reg);  in xhci_restore_registers()
810 	val_64 = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);  in xhci_set_cmd_ring_deq()
819 	xhci_write_64(xhci, val_64, &xhci->op_regs->cmd_ring);  in xhci_set_cmd_ring_deq()
938 	command = readl(&xhci->op_regs->command);  in xhci_suspend()
940 	writel(command, &xhci->op_regs->command);  in xhci_suspend()
945 	if (xhci_handshake(&xhci->op_regs->status,  in xhci_suspend()
957 	command = readl(&xhci->op_regs->command);  in xhci_suspend()
959 	writel(command, &xhci->op_regs->command);  in xhci_suspend()
960 	if (xhci_handshake(&xhci->op_regs->status,  in xhci_suspend()
1024 		command = readl(&xhci->op_regs->command);  in xhci_resume()
1026 		writel(command, &xhci->op_regs->command);  in xhci_resume()
1027 		if (xhci_handshake(&xhci->op_regs->status,  in xhci_resume()
1033 		temp = readl(&xhci->op_regs->status);  in xhci_resume()
1057 		temp = readl(&xhci->op_regs->status);  in xhci_resume()
1058 		writel(temp & ~STS_EINT, &xhci->op_regs->status);  in xhci_resume()
1066 			    readl(&xhci->op_regs->status));  in xhci_resume()
1095 	command = readl(&xhci->op_regs->command);  in xhci_resume()
1097 	writel(command, &xhci->op_regs->command);  in xhci_resume()
1098 	xhci_handshake(&xhci->op_regs->status, STS_HALT,  in xhci_resume()
1115 		status = readl(&xhci->op_regs->status);  in xhci_resume()
1558 	temp = readl(&xhci->op_regs->status);  in xhci_urb_dequeue()
3657 	state = readl(&xhci->op_regs->status);  in xhci_free_dev()
3941 	temp_64 = xhci_read_64(xhci, &xhci->op_regs->dcbaa_ptr);  in xhci_setup_device()
3998 	__le32 __iomem *base_addr = &xhci->op_regs->port_status_base;  in xhci_find_raw_port_number()
4908 	xhci->op_regs = hcd->regs +  in xhci_gen_setup()