Lines Matching refs:val
209 unsigned long val; in set_pts() local
212 val = readl(base + TEGRA_USB_HOSTPC1_DEVLC); in set_pts()
213 val &= ~TEGRA_USB_HOSTPC1_DEVLC_PTS(~0); in set_pts()
214 val |= TEGRA_USB_HOSTPC1_DEVLC_PTS(pts_val); in set_pts()
215 writel(val, base + TEGRA_USB_HOSTPC1_DEVLC); in set_pts()
217 val = readl(base + TEGRA_USB_PORTSC1) & ~TEGRA_PORTSC1_RWC_BITS; in set_pts()
218 val &= ~TEGRA_USB_PORTSC1_PTS(~0); in set_pts()
219 val |= TEGRA_USB_PORTSC1_PTS(pts_val); in set_pts()
220 writel(val, base + TEGRA_USB_PORTSC1); in set_pts()
227 unsigned long val; in set_phcd() local
230 val = readl(base + TEGRA_USB_HOSTPC1_DEVLC); in set_phcd()
232 val |= TEGRA_USB_HOSTPC1_DEVLC_PHCD; in set_phcd()
234 val &= ~TEGRA_USB_HOSTPC1_DEVLC_PHCD; in set_phcd()
235 writel(val, base + TEGRA_USB_HOSTPC1_DEVLC); in set_phcd()
237 val = readl(base + TEGRA_USB_PORTSC1) & ~PORT_RWC_BITS; in set_phcd()
239 val |= TEGRA_USB_PORTSC1_PHCD; in set_phcd()
241 val &= ~TEGRA_USB_PORTSC1_PHCD; in set_phcd()
242 writel(val, base + TEGRA_USB_PORTSC1); in set_phcd()
259 unsigned long val, flags; in utmip_pad_power_on() local
268 val = readl(base + UTMIP_BIAS_CFG0); in utmip_pad_power_on()
269 val &= ~(UTMIP_OTGPD | UTMIP_BIASPD); in utmip_pad_power_on()
272 val &= ~(UTMIP_HSSQUELCH_LEVEL(~0) | in utmip_pad_power_on()
276 val |= UTMIP_HSSQUELCH_LEVEL(config->hssquelch_level); in utmip_pad_power_on()
277 val |= UTMIP_HSDISCON_LEVEL(config->hsdiscon_level); in utmip_pad_power_on()
278 val |= UTMIP_HSDISCON_LEVEL_MSB(config->hsdiscon_level); in utmip_pad_power_on()
280 writel(val, base + UTMIP_BIAS_CFG0); in utmip_pad_power_on()
290 unsigned long val, flags; in utmip_pad_power_off() local
303 val = readl(base + UTMIP_BIAS_CFG0); in utmip_pad_power_off()
304 val |= UTMIP_OTGPD | UTMIP_BIASPD; in utmip_pad_power_off()
305 writel(val, base + UTMIP_BIAS_CFG0); in utmip_pad_power_off()
329 unsigned long val; in utmi_phy_clk_disable() local
333 val = readl(base + USB_SUSP_CTRL); in utmi_phy_clk_disable()
334 val |= USB_SUSP_SET; in utmi_phy_clk_disable()
335 writel(val, base + USB_SUSP_CTRL); in utmi_phy_clk_disable()
339 val = readl(base + USB_SUSP_CTRL); in utmi_phy_clk_disable()
340 val &= ~USB_SUSP_SET; in utmi_phy_clk_disable()
341 writel(val, base + USB_SUSP_CTRL); in utmi_phy_clk_disable()
351 unsigned long val; in utmi_phy_clk_enable() local
355 val = readl(base + USB_SUSP_CTRL); in utmi_phy_clk_enable()
356 val |= USB_SUSP_CLR; in utmi_phy_clk_enable()
357 writel(val, base + USB_SUSP_CTRL); in utmi_phy_clk_enable()
361 val = readl(base + USB_SUSP_CTRL); in utmi_phy_clk_enable()
362 val &= ~USB_SUSP_CLR; in utmi_phy_clk_enable()
363 writel(val, base + USB_SUSP_CTRL); in utmi_phy_clk_enable()
374 unsigned long val; in utmi_phy_power_on() local
378 val = readl(base + USB_SUSP_CTRL); in utmi_phy_power_on()
379 val |= UTMIP_RESET; in utmi_phy_power_on()
380 writel(val, base + USB_SUSP_CTRL); in utmi_phy_power_on()
383 val = readl(base + USB1_LEGACY_CTRL); in utmi_phy_power_on()
384 val |= USB1_NO_LEGACY_MODE; in utmi_phy_power_on()
385 writel(val, base + USB1_LEGACY_CTRL); in utmi_phy_power_on()
388 val = readl(base + UTMIP_TX_CFG0); in utmi_phy_power_on()
389 val |= UTMIP_FS_PREABMLE_J; in utmi_phy_power_on()
390 writel(val, base + UTMIP_TX_CFG0); in utmi_phy_power_on()
392 val = readl(base + UTMIP_HSRX_CFG0); in utmi_phy_power_on()
393 val &= ~(UTMIP_IDLE_WAIT(~0) | UTMIP_ELASTIC_LIMIT(~0)); in utmi_phy_power_on()
394 val |= UTMIP_IDLE_WAIT(config->idle_wait_delay); in utmi_phy_power_on()
395 val |= UTMIP_ELASTIC_LIMIT(config->elastic_limit); in utmi_phy_power_on()
396 writel(val, base + UTMIP_HSRX_CFG0); in utmi_phy_power_on()
398 val = readl(base + UTMIP_HSRX_CFG1); in utmi_phy_power_on()
399 val &= ~UTMIP_HS_SYNC_START_DLY(~0); in utmi_phy_power_on()
400 val |= UTMIP_HS_SYNC_START_DLY(config->hssync_start_delay); in utmi_phy_power_on()
401 writel(val, base + UTMIP_HSRX_CFG1); in utmi_phy_power_on()
403 val = readl(base + UTMIP_DEBOUNCE_CFG0); in utmi_phy_power_on()
404 val &= ~UTMIP_BIAS_DEBOUNCE_A(~0); in utmi_phy_power_on()
405 val |= UTMIP_BIAS_DEBOUNCE_A(phy->freq->debounce); in utmi_phy_power_on()
406 writel(val, base + UTMIP_DEBOUNCE_CFG0); in utmi_phy_power_on()
408 val = readl(base + UTMIP_MISC_CFG0); in utmi_phy_power_on()
409 val &= ~UTMIP_SUSPEND_EXIT_ON_EDGE; in utmi_phy_power_on()
410 writel(val, base + UTMIP_MISC_CFG0); in utmi_phy_power_on()
413 val = readl(base + UTMIP_MISC_CFG1); in utmi_phy_power_on()
414 val &= ~(UTMIP_PLL_ACTIVE_DLY_COUNT(~0) | in utmi_phy_power_on()
416 val |= UTMIP_PLL_ACTIVE_DLY_COUNT(phy->freq->active_delay) | in utmi_phy_power_on()
418 writel(val, base + UTMIP_MISC_CFG1); in utmi_phy_power_on()
420 val = readl(base + UTMIP_PLL_CFG1); in utmi_phy_power_on()
421 val &= ~(UTMIP_XTAL_FREQ_COUNT(~0) | in utmi_phy_power_on()
423 val |= UTMIP_XTAL_FREQ_COUNT(phy->freq->xtal_freq_count) | in utmi_phy_power_on()
425 writel(val, base + UTMIP_PLL_CFG1); in utmi_phy_power_on()
429 val = readl(base + USB_SUSP_CTRL); in utmi_phy_power_on()
430 val &= ~(USB_WAKE_ON_CNNT_EN_DEV | USB_WAKE_ON_DISCON_EN_DEV); in utmi_phy_power_on()
431 writel(val, base + USB_SUSP_CTRL); in utmi_phy_power_on()
433 val = readl(base + UTMIP_BAT_CHRG_CFG0); in utmi_phy_power_on()
434 val &= ~UTMIP_PD_CHRG; in utmi_phy_power_on()
435 writel(val, base + UTMIP_BAT_CHRG_CFG0); in utmi_phy_power_on()
437 val = readl(base + UTMIP_BAT_CHRG_CFG0); in utmi_phy_power_on()
438 val |= UTMIP_PD_CHRG; in utmi_phy_power_on()
439 writel(val, base + UTMIP_BAT_CHRG_CFG0); in utmi_phy_power_on()
444 val = readl(base + UTMIP_XCVR_CFG0); in utmi_phy_power_on()
445 val &= ~(UTMIP_FORCE_PD_POWERDOWN | UTMIP_FORCE_PD2_POWERDOWN | in utmi_phy_power_on()
451 val |= UTMIP_XCVR_SETUP(config->xcvr_setup); in utmi_phy_power_on()
452 val |= UTMIP_XCVR_SETUP_MSB(config->xcvr_setup); in utmi_phy_power_on()
454 val |= UTMIP_XCVR_LSFSLEW(config->xcvr_lsfslew); in utmi_phy_power_on()
455 val |= UTMIP_XCVR_LSRSLEW(config->xcvr_lsrslew); in utmi_phy_power_on()
458 val &= ~(UTMIP_XCVR_HSSLEW(~0) | UTMIP_XCVR_HSSLEW_MSB(~0)); in utmi_phy_power_on()
459 val |= UTMIP_XCVR_HSSLEW(config->xcvr_hsslew); in utmi_phy_power_on()
460 val |= UTMIP_XCVR_HSSLEW_MSB(config->xcvr_hsslew); in utmi_phy_power_on()
462 writel(val, base + UTMIP_XCVR_CFG0); in utmi_phy_power_on()
464 val = readl(base + UTMIP_XCVR_CFG1); in utmi_phy_power_on()
465 val &= ~(UTMIP_FORCE_PDDISC_POWERDOWN | UTMIP_FORCE_PDCHRP_POWERDOWN | in utmi_phy_power_on()
467 val |= UTMIP_XCVR_TERM_RANGE_ADJ(config->term_range_adj); in utmi_phy_power_on()
468 writel(val, base + UTMIP_XCVR_CFG1); in utmi_phy_power_on()
470 val = readl(base + UTMIP_BIAS_CFG1); in utmi_phy_power_on()
471 val &= ~UTMIP_BIAS_PDTRK_COUNT(~0); in utmi_phy_power_on()
472 val |= UTMIP_BIAS_PDTRK_COUNT(0x5); in utmi_phy_power_on()
473 writel(val, base + UTMIP_BIAS_CFG1); in utmi_phy_power_on()
475 val = readl(base + UTMIP_SPARE_CFG0); in utmi_phy_power_on()
477 val |= FUSE_SETUP_SEL; in utmi_phy_power_on()
479 val &= ~FUSE_SETUP_SEL; in utmi_phy_power_on()
480 writel(val, base + UTMIP_SPARE_CFG0); in utmi_phy_power_on()
483 val = readl(base + USB_SUSP_CTRL); in utmi_phy_power_on()
484 val |= UTMIP_PHY_ENABLE; in utmi_phy_power_on()
485 writel(val, base + USB_SUSP_CTRL); in utmi_phy_power_on()
488 val = readl(base + USB_SUSP_CTRL); in utmi_phy_power_on()
489 val &= ~UTMIP_RESET; in utmi_phy_power_on()
490 writel(val, base + USB_SUSP_CTRL); in utmi_phy_power_on()
493 val = readl(base + USB1_LEGACY_CTRL); in utmi_phy_power_on()
494 val &= ~USB1_VBUS_SENSE_CTL_MASK; in utmi_phy_power_on()
495 val |= USB1_VBUS_SENSE_CTL_A_SESS_VLD; in utmi_phy_power_on()
496 writel(val, base + USB1_LEGACY_CTRL); in utmi_phy_power_on()
498 val = readl(base + USB_SUSP_CTRL); in utmi_phy_power_on()
499 val &= ~USB_SUSP_SET; in utmi_phy_power_on()
500 writel(val, base + USB_SUSP_CTRL); in utmi_phy_power_on()
506 val = readl(base + USB_USBMODE); in utmi_phy_power_on()
507 val &= ~USB_USBMODE_MASK; in utmi_phy_power_on()
509 val |= USB_USBMODE_HOST; in utmi_phy_power_on()
511 val |= USB_USBMODE_DEVICE; in utmi_phy_power_on()
512 writel(val, base + USB_USBMODE); in utmi_phy_power_on()
523 unsigned long val; in utmi_phy_power_off() local
529 val = readl(base + USB_SUSP_CTRL); in utmi_phy_power_off()
530 val &= ~USB_WAKEUP_DEBOUNCE_COUNT(~0); in utmi_phy_power_off()
531 val |= USB_WAKE_ON_CNNT_EN_DEV | USB_WAKEUP_DEBOUNCE_COUNT(5); in utmi_phy_power_off()
532 writel(val, base + USB_SUSP_CTRL); in utmi_phy_power_off()
535 val = readl(base + USB_SUSP_CTRL); in utmi_phy_power_off()
536 val |= UTMIP_RESET; in utmi_phy_power_off()
537 writel(val, base + USB_SUSP_CTRL); in utmi_phy_power_off()
539 val = readl(base + UTMIP_BAT_CHRG_CFG0); in utmi_phy_power_off()
540 val |= UTMIP_PD_CHRG; in utmi_phy_power_off()
541 writel(val, base + UTMIP_BAT_CHRG_CFG0); in utmi_phy_power_off()
543 val = readl(base + UTMIP_XCVR_CFG0); in utmi_phy_power_off()
544 val |= UTMIP_FORCE_PD_POWERDOWN | UTMIP_FORCE_PD2_POWERDOWN | in utmi_phy_power_off()
546 writel(val, base + UTMIP_XCVR_CFG0); in utmi_phy_power_off()
548 val = readl(base + UTMIP_XCVR_CFG1); in utmi_phy_power_off()
549 val |= UTMIP_FORCE_PDDISC_POWERDOWN | UTMIP_FORCE_PDCHRP_POWERDOWN | in utmi_phy_power_off()
551 writel(val, base + UTMIP_XCVR_CFG1); in utmi_phy_power_off()
558 unsigned long val; in utmi_phy_preresume() local
561 val = readl(base + UTMIP_TX_CFG0); in utmi_phy_preresume()
562 val |= UTMIP_HS_DISCON_DISABLE; in utmi_phy_preresume()
563 writel(val, base + UTMIP_TX_CFG0); in utmi_phy_preresume()
568 unsigned long val; in utmi_phy_postresume() local
571 val = readl(base + UTMIP_TX_CFG0); in utmi_phy_postresume()
572 val &= ~UTMIP_HS_DISCON_DISABLE; in utmi_phy_postresume()
573 writel(val, base + UTMIP_TX_CFG0); in utmi_phy_postresume()
579 unsigned long val; in utmi_phy_restore_start() local
582 val = readl(base + UTMIP_MISC_CFG0); in utmi_phy_restore_start()
583 val &= ~UTMIP_DPDM_OBSERVE_SEL(~0); in utmi_phy_restore_start()
585 val |= UTMIP_DPDM_OBSERVE_SEL_FS_K; in utmi_phy_restore_start()
587 val |= UTMIP_DPDM_OBSERVE_SEL_FS_J; in utmi_phy_restore_start()
588 writel(val, base + UTMIP_MISC_CFG0); in utmi_phy_restore_start()
591 val = readl(base + UTMIP_MISC_CFG0); in utmi_phy_restore_start()
592 val |= UTMIP_DPDM_OBSERVE; in utmi_phy_restore_start()
593 writel(val, base + UTMIP_MISC_CFG0); in utmi_phy_restore_start()
599 unsigned long val; in utmi_phy_restore_end() local
602 val = readl(base + UTMIP_MISC_CFG0); in utmi_phy_restore_end()
603 val &= ~UTMIP_DPDM_OBSERVE; in utmi_phy_restore_end()
604 writel(val, base + UTMIP_MISC_CFG0); in utmi_phy_restore_end()
611 unsigned long val; in ulpi_phy_power_on() local
631 val = readl(base + USB_SUSP_CTRL); in ulpi_phy_power_on()
632 val |= UHSIC_RESET; in ulpi_phy_power_on()
633 writel(val, base + USB_SUSP_CTRL); in ulpi_phy_power_on()
635 val = readl(base + ULPI_TIMING_CTRL_0); in ulpi_phy_power_on()
636 val |= ULPI_OUTPUT_PINMUX_BYP | ULPI_CLKOUT_PINMUX_BYP; in ulpi_phy_power_on()
637 writel(val, base + ULPI_TIMING_CTRL_0); in ulpi_phy_power_on()
639 val = readl(base + USB_SUSP_CTRL); in ulpi_phy_power_on()
640 val |= ULPI_PHY_ENABLE; in ulpi_phy_power_on()
641 writel(val, base + USB_SUSP_CTRL); in ulpi_phy_power_on()
643 val = 0; in ulpi_phy_power_on()
644 writel(val, base + ULPI_TIMING_CTRL_1); in ulpi_phy_power_on()
646 val |= ULPI_DATA_TRIMMER_SEL(4); in ulpi_phy_power_on()
647 val |= ULPI_STPDIRNXT_TRIMMER_SEL(4); in ulpi_phy_power_on()
648 val |= ULPI_DIR_TRIMMER_SEL(4); in ulpi_phy_power_on()
649 writel(val, base + ULPI_TIMING_CTRL_1); in ulpi_phy_power_on()
652 val |= ULPI_DATA_TRIMMER_LOAD; in ulpi_phy_power_on()
653 val |= ULPI_STPDIRNXT_TRIMMER_LOAD; in ulpi_phy_power_on()
654 val |= ULPI_DIR_TRIMMER_LOAD; in ulpi_phy_power_on()
655 writel(val, base + ULPI_TIMING_CTRL_1); in ulpi_phy_power_on()
670 val = readl(base + USB_SUSP_CTRL); in ulpi_phy_power_on()
671 val |= USB_SUSP_CLR; in ulpi_phy_power_on()
672 writel(val, base + USB_SUSP_CTRL); in ulpi_phy_power_on()
675 val = readl(base + USB_SUSP_CTRL); in ulpi_phy_power_on()
676 val &= ~USB_SUSP_CLR; in ulpi_phy_power_on()
677 writel(val, base + USB_SUSP_CTRL); in ulpi_phy_power_on()