569 #define aty_ld_le32(regindex)		_aty_ld_le32(regindex, par)  macro
586 	return aty_ld_le32(CLOCK_CNTL_DATA);  in _aty_ld_pll()
637 	val = aty_ld_le32(BIOS_0_SCRATCH);  in register_test()
640 	if (aty_ld_le32(BIOS_0_SCRATCH) == 0x55555555) {  in register_test()
643 		if (aty_ld_le32(BIOS_0_SCRATCH) == 0xAAAAAAAA)  in register_test()
661 			par->fifo_slots = aty_ld_le32(GUI_STAT) & 0x0fff;  in do_wait_for_fifo()
678 			if (!(aty_ld_le32(GUI_STAT) & (1 << 31))) {  in wait_for_idle()
702 	tmp = aty_ld_le32(PC_NGUI_CTLSTAT);  in aty128_flush_pixel_cache()
708 		if (!(aty_ld_le32(PC_NGUI_CTLSTAT) & PC_BUSY))  in aty128_flush_pixel_cache()
719 	clock_cntl_index = aty_ld_le32(CLOCK_CNTL_INDEX);  in aty128_reset_engine()
724 	gen_reset_cntl = aty_ld_le32(GEN_RESET_CNTL);  in aty128_reset_engine()
726 	aty_ld_le32(GEN_RESET_CNTL);  in aty128_reset_engine()
728 	aty_ld_le32(GEN_RESET_CNTL);  in aty128_reset_engine()
841 	temp = aty_ld_le32(RAGE128_MPP_TB_CONFIG);  in aty128_map_ROM()
845 	temp = aty_ld_le32(RAGE128_MPP_TB_CONFIG);  in aty128_map_ROM()
1015 	switch (aty_ld_le32(MEM_CNTL) & 0x3) {  in aty128_timings()
1303 		aty_st_le32(CRTC_EXT_CNTL, aty_ld_le32(CRTC_EXT_CNTL) |  in aty128_set_crt_enable()
1305 		aty_st_le32(DAC_CNTL, (aty_ld_le32(DAC_CNTL) |  in aty128_set_crt_enable()
1308 		aty_st_le32(CRTC_EXT_CNTL, aty_ld_le32(CRTC_EXT_CNTL) &  in aty128_set_crt_enable()
1320 		reg = aty_ld_le32(LVDS_GEN_CNTL);  in aty128_set_lcd_enable()
1331 		reg = aty_ld_le32(LVDS_GEN_CNTL);  in aty128_set_lcd_enable()
1349 	aty_st_le32(CLOCK_CNTL_INDEX, aty_ld_le32(CLOCK_CNTL_INDEX) | (3 << 8));  in aty128_set_pll()
1535 	config = aty_ld_le32(CNFG_CNTL) & ~3;  in aty128fb_set_par()
1685 		aty_st_le32(DAC_CNTL, aty_ld_le32(DAC_CNTL) |  in aty128_st_pal()
1690 		aty_st_le32(DAC_CNTL, aty_ld_le32(DAC_CNTL) &  in aty128_st_pal()
1800 	unsigned int reg = aty_ld_le32(LVDS_GEN_CNTL);  in aty128_bl_update_status()
1816 			aty_ld_le32(LVDS_GEN_CNTL);  in aty128_bl_update_status()
1830 		aty_st_le32(DAC_CNTL, aty_ld_le32(DAC_CNTL) & (~DAC_PDWN));  in aty128_bl_update_status()
1839 		aty_ld_le32(LVDS_GEN_CNTL);  in aty128_bl_update_status()
1845 		aty_st_le32(DAC_CNTL, aty_ld_le32(DAC_CNTL) | DAC_PDWN);  in aty128_bl_update_status()
1944 	chip_rev = (aty_ld_le32(CNFG_CNTL) >> 16) & 0x1F;  in aty128_init()
2046 	dac = aty_ld_le32(DAC_CNTL);  in aty128_init()
2054 	aty_st_le32(BUS_CNTL, aty_ld_le32(BUS_CNTL) | BUS_MASTER_DIS);  in aty128_init()
2133 	par->vram_size = aty_ld_le32(CNFG_MEMSIZE) & 0x03FFFFFF;  in aty128_probe()
2399 	save_dp_datatype = aty_ld_le32(DP_DATATYPE);
2400 	save_dp_cntl     = aty_ld_le32(DP_CNTL);
2457 		aty_st_le32(CRTC2_GEN_CNTL, aty_ld_le32(CRTC2_GEN_CNTL) &  in aty128_set_suspend()