1202 			       struct radeon_regs *save)  in radeon_save_state()  argument
1205 	save->crtc_gen_cntl = INREG(CRTC_GEN_CNTL);  in radeon_save_state()
1206 	save->crtc_ext_cntl = INREG(CRTC_EXT_CNTL);  in radeon_save_state()
1207 	save->crtc_more_cntl = INREG(CRTC_MORE_CNTL);  in radeon_save_state()
1208 	save->dac_cntl = INREG(DAC_CNTL);  in radeon_save_state()
1209         save->crtc_h_total_disp = INREG(CRTC_H_TOTAL_DISP);  in radeon_save_state()
1210         save->crtc_h_sync_strt_wid = INREG(CRTC_H_SYNC_STRT_WID);  in radeon_save_state()
1211         save->crtc_v_total_disp = INREG(CRTC_V_TOTAL_DISP);  in radeon_save_state()
1212         save->crtc_v_sync_strt_wid = INREG(CRTC_V_SYNC_STRT_WID);  in radeon_save_state()
1213 	save->crtc_pitch = INREG(CRTC_PITCH);  in radeon_save_state()
1214 	save->surface_cntl = INREG(SURFACE_CNTL);  in radeon_save_state()
1217 	save->fp_crtc_h_total_disp = INREG(FP_CRTC_H_TOTAL_DISP);  in radeon_save_state()
1218 	save->fp_crtc_v_total_disp = INREG(FP_CRTC_V_TOTAL_DISP);  in radeon_save_state()
1219 	save->fp_gen_cntl = INREG(FP_GEN_CNTL);  in radeon_save_state()
1220 	save->fp_h_sync_strt_wid = INREG(FP_H_SYNC_STRT_WID);  in radeon_save_state()
1221 	save->fp_horz_stretch = INREG(FP_HORZ_STRETCH);  in radeon_save_state()
1222 	save->fp_v_sync_strt_wid = INREG(FP_V_SYNC_STRT_WID);  in radeon_save_state()
1223 	save->fp_vert_stretch = INREG(FP_VERT_STRETCH);  in radeon_save_state()
1224 	save->lvds_gen_cntl = INREG(LVDS_GEN_CNTL);  in radeon_save_state()
1225 	save->lvds_pll_cntl = INREG(LVDS_PLL_CNTL);  in radeon_save_state()
1226 	save->tmds_crc = INREG(TMDS_CRC);  in radeon_save_state()
1227 	save->tmds_transmitter_cntl = INREG(TMDS_TRANSMITTER_CNTL);  in radeon_save_state()
1228 	save->vclk_ecp_cntl = INPLL(VCLK_ECP_CNTL);  in radeon_save_state()
1231 	save->clk_cntl_index = INREG(CLOCK_CNTL_INDEX) & ~0x3f;  in radeon_save_state()
1233 	save->ppll_div_3 = INPLL(PPLL_DIV_3);  in radeon_save_state()
1234 	save->ppll_ref_div = INPLL(PPLL_REF_DIV);  in radeon_save_state()