78 	struct mipi_dsim_device *dsim = dev_id;  in exynos_mipi_dsi_interrupt_handler()  local
81 	intsrc = exynos_mipi_dsi_read_interrupt(dsim);  in exynos_mipi_dsi_interrupt_handler()
82 	intmsk = exynos_mipi_dsi_read_interrupt_mask(dsim);  in exynos_mipi_dsi_interrupt_handler()
87 		dev_dbg(dsim->dev, "MIPI INTMSK_RX_DONE\n");  in exynos_mipi_dsi_interrupt_handler()
91 		dev_dbg(dsim->dev, "MIPI INTMSK_FIFO_EMPTY\n");  in exynos_mipi_dsi_interrupt_handler()
94 	exynos_mipi_dsi_clear_interrupt(dsim, intmsk);  in exynos_mipi_dsi_interrupt_handler()
105 static void exynos_mipi_dsi_long_data_wr(struct mipi_dsim_device *dsim,  in exynos_mipi_dsi_long_data_wr()  argument
121 			dev_dbg(dsim->dev, "count = 3 payload = %x, %x %x %x\n",  in exynos_mipi_dsi_long_data_wr()
128 			dev_dbg(dsim->dev,  in exynos_mipi_dsi_long_data_wr()
136 			exynos_mipi_dsi_wr_tx_data(dsim, payload);  in exynos_mipi_dsi_long_data_wr()
144 			dev_dbg(dsim->dev,  in exynos_mipi_dsi_long_data_wr()
151 			exynos_mipi_dsi_wr_tx_data(dsim, payload);  in exynos_mipi_dsi_long_data_wr()
156 int exynos_mipi_dsi_wr_data(struct mipi_dsim_device *dsim, unsigned int data_id,  in exynos_mipi_dsi_wr_data()  argument
161 	if (dsim->state == DSIM_STATE_ULPS) {  in exynos_mipi_dsi_wr_data()
162 		dev_err(dsim->dev, "state is ULPS.\n");  in exynos_mipi_dsi_wr_data()
170 	mutex_lock(&dsim->lock);  in exynos_mipi_dsi_wr_data()
180 		exynos_mipi_dsi_wr_tx_header(dsim, data_id, data0[0], data0[1]);  in exynos_mipi_dsi_wr_data()
183 			mutex_unlock(&dsim->lock);  in exynos_mipi_dsi_wr_data()
186 			mutex_unlock(&dsim->lock);  in exynos_mipi_dsi_wr_data()
195 		exynos_mipi_dsi_wr_tx_header(dsim, data_id, data0[0], data0[1]);  in exynos_mipi_dsi_wr_data()
198 			mutex_unlock(&dsim->lock);  in exynos_mipi_dsi_wr_data()
201 			mutex_unlock(&dsim->lock);  in exynos_mipi_dsi_wr_data()
211 		mutex_unlock(&dsim->lock);  in exynos_mipi_dsi_wr_data()
217 		mutex_unlock(&dsim->lock);  in exynos_mipi_dsi_wr_data()
233 			exynos_mipi_dsi_wr_tx_data(dsim, payload);  in exynos_mipi_dsi_wr_data()
235 			dev_dbg(dsim->dev, "count = %d payload = %x,%x %x %x\n",  in exynos_mipi_dsi_wr_data()
241 			exynos_mipi_dsi_long_data_wr(dsim, data0, data_size);  in exynos_mipi_dsi_wr_data()
244 		exynos_mipi_dsi_wr_tx_header(dsim, data_id, data_size & 0xff,  in exynos_mipi_dsi_wr_data()
249 			dev_warn(dsim->dev, "command write timeout.\n");  in exynos_mipi_dsi_wr_data()
250 			mutex_unlock(&dsim->lock);  in exynos_mipi_dsi_wr_data()
256 			mutex_unlock(&dsim->lock);  in exynos_mipi_dsi_wr_data()
259 			mutex_unlock(&dsim->lock);  in exynos_mipi_dsi_wr_data()
271 			mutex_unlock(&dsim->lock);  in exynos_mipi_dsi_wr_data()
274 			mutex_unlock(&dsim->lock);  in exynos_mipi_dsi_wr_data()
278 		dev_warn(dsim->dev,  in exynos_mipi_dsi_wr_data()
282 		mutex_unlock(&dsim->lock);  in exynos_mipi_dsi_wr_data()
287 static unsigned int exynos_mipi_dsi_long_data_rd(struct mipi_dsim_device *dsim,  in exynos_mipi_dsi_long_data_rd()  argument
295 	dev_dbg(dsim->dev, "mipi dsi rx size : %d\n", rxsize);  in exynos_mipi_dsi_long_data_rd()
297 		dev_dbg(dsim->dev,  in exynos_mipi_dsi_long_data_rd()
304 		rcv_pkt = exynos_mipi_dsi_rd_rx_fifo(dsim);  in exynos_mipi_dsi_long_data_rd()
305 		dev_dbg(dsim->dev, "received pkt : %08x\n", rcv_pkt);  in exynos_mipi_dsi_long_data_rd()
309 			dev_dbg(dsim->dev, "received value : %02x\n",  in exynos_mipi_dsi_long_data_rd()
314 		rcv_pkt = exynos_mipi_dsi_rd_rx_fifo(dsim);  in exynos_mipi_dsi_long_data_rd()
315 		dev_dbg(dsim->dev, "received pkt : %08x\n", rcv_pkt);  in exynos_mipi_dsi_long_data_rd()
319 			dev_dbg(dsim->dev, "received value : %02x\n",  in exynos_mipi_dsi_long_data_rd()
342 int exynos_mipi_dsi_rd_data(struct mipi_dsim_device *dsim, unsigned int data_id,  in exynos_mipi_dsi_rd_data()  argument
349 	if (dsim->state == DSIM_STATE_ULPS) {  in exynos_mipi_dsi_rd_data()
350 		dev_err(dsim->dev, "state is ULPS.\n");  in exynos_mipi_dsi_rd_data()
358 	mutex_lock(&dsim->lock);  in exynos_mipi_dsi_rd_data()
360 	exynos_mipi_dsi_rd_tx_header(dsim,  in exynos_mipi_dsi_rd_data()
370 		exynos_mipi_dsi_rd_tx_header(dsim,  in exynos_mipi_dsi_rd_data()
375 		dev_warn(dsim->dev,  in exynos_mipi_dsi_rd_data()
379 		mutex_unlock(&dsim->lock);  in exynos_mipi_dsi_rd_data()
386 		mutex_unlock(&dsim->lock);  in exynos_mipi_dsi_rd_data()
392 	rx_data = exynos_mipi_dsi_rd_rx_fifo(dsim);  in exynos_mipi_dsi_rd_data()
408 		rxsize = exynos_mipi_dsi_long_data_rd(dsim, req_size, rx_data,  in exynos_mipi_dsi_rd_data()
414 	rcv_pkt = exynos_mipi_dsi_rd_rx_fifo(dsim);  in exynos_mipi_dsi_rd_data()
419 		dev_info(dsim->dev,  in exynos_mipi_dsi_rd_data()
424 	mutex_unlock(&dsim->lock);  in exynos_mipi_dsi_rd_data()
431 		rcv_pkt = exynos_mipi_dsi_rd_rx_fifo(dsim);  in exynos_mipi_dsi_rd_data()
435 		dev_dbg(dsim->dev,  in exynos_mipi_dsi_rd_data()
439 	dev_info(dsim->dev,  in exynos_mipi_dsi_rd_data()
442 	mutex_unlock(&dsim->lock);  in exynos_mipi_dsi_rd_data()
447 static int exynos_mipi_dsi_pll_on(struct mipi_dsim_device *dsim,  in exynos_mipi_dsi_pll_on()  argument
455 		exynos_mipi_dsi_enable_pll(dsim, 1);  in exynos_mipi_dsi_pll_on()
458 			if (exynos_mipi_dsi_is_pll_stable(dsim))  in exynos_mipi_dsi_pll_on()
464 		exynos_mipi_dsi_enable_pll(dsim, 0);  in exynos_mipi_dsi_pll_on()
469 static unsigned long exynos_mipi_dsi_change_pll(struct mipi_dsim_device *dsim,  in exynos_mipi_dsi_change_pll()  argument
499 		dev_warn(dsim->dev, "fin_pll range should be 6MHz ~ 12MHz\n");  in exynos_mipi_dsi_change_pll()
500 		exynos_mipi_dsi_enable_afc(dsim, 0, 0);  in exynos_mipi_dsi_change_pll()
503 			exynos_mipi_dsi_enable_afc(dsim, 1, 0x1);  in exynos_mipi_dsi_change_pll()
505 			exynos_mipi_dsi_enable_afc(dsim, 1, 0x0);  in exynos_mipi_dsi_change_pll()
507 			exynos_mipi_dsi_enable_afc(dsim, 1, 0x3);  in exynos_mipi_dsi_change_pll()
509 			exynos_mipi_dsi_enable_afc(dsim, 1, 0x2);  in exynos_mipi_dsi_change_pll()
511 			exynos_mipi_dsi_enable_afc(dsim, 1, 0x5);  in exynos_mipi_dsi_change_pll()
513 			exynos_mipi_dsi_enable_afc(dsim, 1, 0x4);  in exynos_mipi_dsi_change_pll()
517 	dev_dbg(dsim->dev, "dfvco = %lu, dfin_pll = %lu, main_divider = %d\n",  in exynos_mipi_dsi_change_pll()
520 		dev_warn(dsim->dev, "fvco range should be 500MHz ~ 1000MHz\n");  in exynos_mipi_dsi_change_pll()
523 	dev_dbg(dsim->dev, "dpll_out = %lu, dfvco = %lu, scaler = %d\n",  in exynos_mipi_dsi_change_pll()
533 	dev_dbg(dsim->dev, "freq_band = %d\n", freq_band);  in exynos_mipi_dsi_change_pll()
535 	exynos_mipi_dsi_pll_freq(dsim, pre_divider, main_divider, scaler);  in exynos_mipi_dsi_change_pll()
537 	exynos_mipi_dsi_hs_zero_ctrl(dsim, 0);  in exynos_mipi_dsi_change_pll()
538 	exynos_mipi_dsi_prep_ctrl(dsim, 0);  in exynos_mipi_dsi_change_pll()
541 	exynos_mipi_dsi_pll_freq_band(dsim, freq_band);  in exynos_mipi_dsi_change_pll()
544 	exynos_mipi_dsi_pll_stable_time(dsim, dsim->dsim_config->pll_stable_time);  in exynos_mipi_dsi_change_pll()
547 	dev_dbg(dsim->dev, "FOUT of mipi dphy pll is %luMHz\n",  in exynos_mipi_dsi_change_pll()
553 static int exynos_mipi_dsi_set_clock(struct mipi_dsim_device *dsim,  in exynos_mipi_dsi_set_clock()  argument
561 		dsim->e_clk_src = byte_clk_sel;  in exynos_mipi_dsi_set_clock()
564 		exynos_mipi_dsi_set_byte_clock_src(dsim, byte_clk_sel);  in exynos_mipi_dsi_set_clock()
568 			hs_clk = exynos_mipi_dsi_change_pll(dsim,  in exynos_mipi_dsi_set_clock()
569 				dsim->dsim_config->p, dsim->dsim_config->m,  in exynos_mipi_dsi_set_clock()
570 				dsim->dsim_config->s);  in exynos_mipi_dsi_set_clock()
572 				dev_err(dsim->dev,  in exynos_mipi_dsi_set_clock()
578 			exynos_mipi_dsi_enable_pll_bypass(dsim, 0);  in exynos_mipi_dsi_set_clock()
579 			exynos_mipi_dsi_pll_on(dsim, 1);  in exynos_mipi_dsi_set_clock()
582 			dev_warn(dsim->dev, "this project is not support\n");  in exynos_mipi_dsi_set_clock()
583 			dev_warn(dsim->dev,  in exynos_mipi_dsi_set_clock()
586 			dev_warn(dsim->dev, "this project is not support\n");  in exynos_mipi_dsi_set_clock()
587 			dev_warn(dsim->dev,  in exynos_mipi_dsi_set_clock()
592 		esc_div = byte_clk / (dsim->dsim_config->esc_clk);  in exynos_mipi_dsi_set_clock()
593 		dev_dbg(dsim->dev,  in exynos_mipi_dsi_set_clock()
595 			esc_div, byte_clk, dsim->dsim_config->esc_clk);  in exynos_mipi_dsi_set_clock()
598 					dsim->dsim_config->esc_clk)  in exynos_mipi_dsi_set_clock()
602 		dev_dbg(dsim->dev,  in exynos_mipi_dsi_set_clock()
607 		exynos_mipi_dsi_enable_byte_clock(dsim, 1);  in exynos_mipi_dsi_set_clock()
610 		exynos_mipi_dsi_set_esc_clk_prs(dsim, 1, esc_div);  in exynos_mipi_dsi_set_clock()
612 		exynos_mipi_dsi_enable_esc_clk_on_lane(dsim,  in exynos_mipi_dsi_set_clock()
613 			(DSIM_LANE_CLOCK | dsim->data_lane), 1);  in exynos_mipi_dsi_set_clock()
615 		dev_dbg(dsim->dev, "byte clock is %luMHz\n",  in exynos_mipi_dsi_set_clock()
617 		dev_dbg(dsim->dev, "escape clock that user's need is %lu\n",  in exynos_mipi_dsi_set_clock()
618 			(dsim->dsim_config->esc_clk / MHZ));  in exynos_mipi_dsi_set_clock()
619 		dev_dbg(dsim->dev, "escape clock divider is %x\n", esc_div);  in exynos_mipi_dsi_set_clock()
620 		dev_dbg(dsim->dev, "escape clock is %luMHz\n",  in exynos_mipi_dsi_set_clock()
626 			dev_warn(dsim->dev, "error rate is %lu over.\n",  in exynos_mipi_dsi_set_clock()
631 			dev_warn(dsim->dev, "error rate is %lu under.\n",  in exynos_mipi_dsi_set_clock()
635 		exynos_mipi_dsi_enable_esc_clk_on_lane(dsim,  in exynos_mipi_dsi_set_clock()
636 			(DSIM_LANE_CLOCK | dsim->data_lane), 0);  in exynos_mipi_dsi_set_clock()
637 		exynos_mipi_dsi_set_esc_clk_prs(dsim, 0, 0);  in exynos_mipi_dsi_set_clock()
640 		exynos_mipi_dsi_enable_byte_clock(dsim, 0);  in exynos_mipi_dsi_set_clock()
643 			exynos_mipi_dsi_pll_on(dsim, 0);  in exynos_mipi_dsi_set_clock()
649 int exynos_mipi_dsi_init_dsim(struct mipi_dsim_device *dsim)  in exynos_mipi_dsi_init_dsim()  argument
651 	dsim->state = DSIM_STATE_INIT;  in exynos_mipi_dsi_init_dsim()
653 	switch (dsim->dsim_config->e_no_data_lane) {  in exynos_mipi_dsi_init_dsim()
655 		dsim->data_lane = DSIM_LANE_DATA0;  in exynos_mipi_dsi_init_dsim()
658 		dsim->data_lane = DSIM_LANE_DATA0 | DSIM_LANE_DATA1;  in exynos_mipi_dsi_init_dsim()
661 		dsim->data_lane = DSIM_LANE_DATA0 | DSIM_LANE_DATA1 |  in exynos_mipi_dsi_init_dsim()
665 		dsim->data_lane = DSIM_LANE_DATA0 | DSIM_LANE_DATA1 |  in exynos_mipi_dsi_init_dsim()
669 		dev_info(dsim->dev, "data lane is invalid.\n");  in exynos_mipi_dsi_init_dsim()
673 	exynos_mipi_dsi_sw_reset(dsim);  in exynos_mipi_dsi_init_dsim()
674 	exynos_mipi_dsi_func_reset(dsim);  in exynos_mipi_dsi_init_dsim()
676 	exynos_mipi_dsi_dp_dn_swap(dsim, 0);  in exynos_mipi_dsi_init_dsim()
681 void exynos_mipi_dsi_init_interrupt(struct mipi_dsim_device *dsim)  in exynos_mipi_dsi_init_interrupt()  argument
686 	exynos_mipi_dsi_set_interrupt(dsim, src, 1);  in exynos_mipi_dsi_init_interrupt()
690 	exynos_mipi_dsi_set_interrupt_mask(dsim, src, 1);  in exynos_mipi_dsi_init_interrupt()
693 int exynos_mipi_dsi_enable_frame_done_int(struct mipi_dsim_device *dsim,  in exynos_mipi_dsi_enable_frame_done_int()  argument
697 	exynos_mipi_dsi_set_interrupt_mask(dsim, INTMSK_FRAME_DONE, enable);  in exynos_mipi_dsi_enable_frame_done_int()
702 void exynos_mipi_dsi_stand_by(struct mipi_dsim_device *dsim,  in exynos_mipi_dsi_stand_by()  argument
708 	exynos_mipi_dsi_set_main_stand_by(dsim, enable);  in exynos_mipi_dsi_stand_by()
711 int exynos_mipi_dsi_set_display_mode(struct mipi_dsim_device *dsim,  in exynos_mipi_dsi_set_display_mode()  argument
717 	dsim_pd = (struct mipi_dsim_platform_data *)dsim->pd;  in exynos_mipi_dsi_set_display_mode()
723 			exynos_mipi_dsi_set_main_disp_vporch(dsim,  in exynos_mipi_dsi_set_display_mode()
727 			exynos_mipi_dsi_set_main_disp_hporch(dsim,  in exynos_mipi_dsi_set_display_mode()
730 			exynos_mipi_dsi_set_main_disp_sync_area(dsim,  in exynos_mipi_dsi_set_display_mode()
736 	exynos_mipi_dsi_set_main_disp_resol(dsim, timing->xres,  in exynos_mipi_dsi_set_display_mode()
739 	exynos_mipi_dsi_display_config(dsim, dsim_config);  in exynos_mipi_dsi_set_display_mode()
741 	dev_info(dsim->dev, "lcd panel ==> width = %d, height = %d\n",  in exynos_mipi_dsi_set_display_mode()
747 int exynos_mipi_dsi_init_link(struct mipi_dsim_device *dsim)  in exynos_mipi_dsi_init_link()  argument
751 	switch (dsim->state) {  in exynos_mipi_dsi_init_link()
753 		exynos_mipi_dsi_init_fifo_pointer(dsim, 0x1f);  in exynos_mipi_dsi_init_link()
756 		exynos_mipi_dsi_init_config(dsim);  in exynos_mipi_dsi_init_link()
757 		exynos_mipi_dsi_enable_lane(dsim, DSIM_LANE_CLOCK, 1);  in exynos_mipi_dsi_init_link()
758 		exynos_mipi_dsi_enable_lane(dsim, dsim->data_lane, 1);  in exynos_mipi_dsi_init_link()
761 		exynos_mipi_dsi_set_clock(dsim, dsim->dsim_config->e_byte_clk, 1);  in exynos_mipi_dsi_init_link()
764 		while (!(exynos_mipi_dsi_is_lane_state(dsim))) {  in exynos_mipi_dsi_init_link()
767 				dev_err(dsim->dev,  in exynos_mipi_dsi_init_link()
769 				dev_err(dsim->dev,  in exynos_mipi_dsi_init_link()
776 			dev_info(dsim->dev,  in exynos_mipi_dsi_init_link()
778 			dev_info(dsim->dev, "DSI Master state is stop state\n");  in exynos_mipi_dsi_init_link()
781 		dsim->state = DSIM_STATE_STOP;  in exynos_mipi_dsi_init_link()
784 		exynos_mipi_dsi_set_stop_state_counter(dsim,  in exynos_mipi_dsi_init_link()
785 			dsim->dsim_config->stop_holding_cnt);  in exynos_mipi_dsi_init_link()
786 		exynos_mipi_dsi_set_bta_timeout(dsim,  in exynos_mipi_dsi_init_link()
787 			dsim->dsim_config->bta_timeout);  in exynos_mipi_dsi_init_link()
788 		exynos_mipi_dsi_set_lpdr_timeout(dsim,  in exynos_mipi_dsi_init_link()
789 			dsim->dsim_config->rx_timeout);  in exynos_mipi_dsi_init_link()
793 		dev_info(dsim->dev, "DSI Master is already init.\n");  in exynos_mipi_dsi_init_link()
800 int exynos_mipi_dsi_set_hs_enable(struct mipi_dsim_device *dsim)  in exynos_mipi_dsi_set_hs_enable()  argument
802 	if (dsim->state != DSIM_STATE_STOP) {  in exynos_mipi_dsi_set_hs_enable()
803 		dev_warn(dsim->dev, "DSIM is not in stop state.\n");  in exynos_mipi_dsi_set_hs_enable()
807 	if (dsim->e_clk_src == DSIM_EXT_CLK_BYPASS) {  in exynos_mipi_dsi_set_hs_enable()
808 		dev_warn(dsim->dev, "clock source is external bypass.\n");  in exynos_mipi_dsi_set_hs_enable()
812 	dsim->state = DSIM_STATE_HSCLKEN;  in exynos_mipi_dsi_set_hs_enable()
815 	exynos_mipi_dsi_set_lcdc_transfer_mode(dsim, 0);  in exynos_mipi_dsi_set_hs_enable()
816 	exynos_mipi_dsi_set_cpu_transfer_mode(dsim, 0);  in exynos_mipi_dsi_set_hs_enable()
817 	exynos_mipi_dsi_enable_hs_clock(dsim, 1);  in exynos_mipi_dsi_set_hs_enable()
822 int exynos_mipi_dsi_set_data_transfer_mode(struct mipi_dsim_device *dsim,  in exynos_mipi_dsi_set_data_transfer_mode()  argument
826 		if (dsim->state != DSIM_STATE_HSCLKEN) {  in exynos_mipi_dsi_set_data_transfer_mode()
827 			dev_err(dsim->dev, "HS Clock lane is not enabled.\n");  in exynos_mipi_dsi_set_data_transfer_mode()
831 		exynos_mipi_dsi_set_lcdc_transfer_mode(dsim, 0);  in exynos_mipi_dsi_set_data_transfer_mode()
833 		if (dsim->state == DSIM_STATE_INIT || dsim->state ==  in exynos_mipi_dsi_set_data_transfer_mode()
835 			dev_err(dsim->dev,  in exynos_mipi_dsi_set_data_transfer_mode()
840 		exynos_mipi_dsi_set_cpu_transfer_mode(dsim, 0);  in exynos_mipi_dsi_set_data_transfer_mode()
846 int exynos_mipi_dsi_get_frame_done_status(struct mipi_dsim_device *dsim)  in exynos_mipi_dsi_get_frame_done_status()  argument
848 	return _exynos_mipi_dsi_get_frame_done_status(dsim);  in exynos_mipi_dsi_get_frame_done_status()
851 int exynos_mipi_dsi_clear_frame_done(struct mipi_dsim_device *dsim)  in exynos_mipi_dsi_clear_frame_done()  argument
853 	_exynos_mipi_dsi_clear_frame_done(dsim);  in exynos_mipi_dsi_clear_frame_done()
858 int exynos_mipi_dsi_fifo_clear(struct mipi_dsim_device *dsim,  in exynos_mipi_dsi_fifo_clear()  argument
863 	exynos_mipi_dsi_sw_reset_release(dsim);  in exynos_mipi_dsi_fifo_clear()
864 	exynos_mipi_dsi_func_reset(dsim);  in exynos_mipi_dsi_fifo_clear()
867 		if (exynos_mipi_dsi_get_sw_reset_release(dsim)) {  in exynos_mipi_dsi_fifo_clear()
868 			exynos_mipi_dsi_init_interrupt(dsim);  in exynos_mipi_dsi_fifo_clear()
869 			dev_dbg(dsim->dev, "reset release done.\n");  in exynos_mipi_dsi_fifo_clear()
874 	dev_err(dsim->dev, "failed to clear dsim fifo.\n");  in exynos_mipi_dsi_fifo_clear()