Lines Matching refs:NV_RD32
83 NV_WR32(par->PRAMDAC, 0x0300, NV_RD32(par->PRAMDAC, 0x0300)); in NVShowHideCursor()
147 pll = NV_RD32(par->PMC, 0x4020); in nvGetClocks()
149 pll = NV_RD32(par->PMC, 0x4024); in nvGetClocks()
162 pll = NV_RD32(par->PMC, 0x4000); in nvGetClocks()
164 pll = NV_RD32(par->PMC, 0x4004); in nvGetClocks()
172 pll = NV_RD32(par->PRAMDAC0, 0x0504); in nvGetClocks()
176 pll = NV_RD32(par->PRAMDAC0, 0x0574); in nvGetClocks()
186 pll = NV_RD32(par->PRAMDAC0, 0x0500); in nvGetClocks()
190 pll = NV_RD32(par->PRAMDAC0, 0x0570); in nvGetClocks()
202 pll = NV_RD32(par->PRAMDAC0, 0x0504); in nvGetClocks()
215 pll = NV_RD32(par->PRAMDAC0, 0x0500); in nvGetClocks()
228 pll = NV_RD32(par->PRAMDAC0, 0x0504); in nvGetClocks()
234 pll = NV_RD32(par->PRAMDAC0, 0x0500); in nvGetClocks()
391 cfg1 = NV_RD32(par->PFB, 0x00000204); in nv4UpdateArbitrationSettings()
395 sim_data.memory_width = (NV_RD32(par->PEXTDEV, 0x0000) & 0x10) ? in nv4UpdateArbitrationSettings()
630 cfg1 = NV_RD32(par->PFB, 0x0204); in nv10UpdateArbitrationSettings()
634 sim_data.memory_type = (NV_RD32(par->PFB, 0x0200) & 0x01) ? 1 : 0; in nv10UpdateArbitrationSettings()
635 sim_data.memory_width = (NV_RD32(par->PEXTDEV, 0x0000) & 0x10) ? in nv10UpdateArbitrationSettings()
702 pll = NV_RD32(par->PRAMDAC0, 0x0500); in nForceUpdateArbitrationSettings()
896 state->control = NV_RD32(par->PRAMDAC0, 0x0580) & in NVCalcStateExt()
932 state->config = NV_RD32(par->PFB, 0x00000200); in NVCalcStateExt()
1059 NV_RD32(par->PRAMIN, 0x080A * 4) | 0x01000000); in NVLoadStateExt()
1061 NV_RD32(par->PRAMIN, 0x0812 * 4) | 0x01000000); in NVLoadStateExt()
1063 NV_RD32(par->PRAMIN, 0x081A * 4) | 0x01000000); in NVLoadStateExt()
1065 NV_RD32(par->PRAMIN, 0x0822 * 4) | 0x01000000); in NVLoadStateExt()
1067 NV_RD32(par->PRAMIN, 0x082A * 4) | 0x01000000); in NVLoadStateExt()
1069 NV_RD32(par->PRAMIN, 0x0832 * 4) | 0x01000000); in NVLoadStateExt()
1071 NV_RD32(par->PRAMIN, 0x083A * 4) | 0x01000000); in NVLoadStateExt()
1073 NV_RD32(par->PRAMIN, 0x0842 * 4) | 0x01000000); in NVLoadStateExt()
1143 NV_RD32(par->PRAMIN, 0x0804 * 4) | 0x00080000); in NVLoadStateExt()
1145 NV_RD32(par->PRAMIN, 0x0808 * 4) | 0x00080000); in NVLoadStateExt()
1147 NV_RD32(par->PRAMIN, 0x080C * 4) | 0x00080000); in NVLoadStateExt()
1149 NV_RD32(par->PRAMIN, 0x0810 * 4) | 0x00080000); in NVLoadStateExt()
1151 NV_RD32(par->PRAMIN, 0x0814 * 4) | 0x00080000); in NVLoadStateExt()
1153 NV_RD32(par->PRAMIN, 0x0818 * 4) | 0x00080000); in NVLoadStateExt()
1155 NV_RD32(par->PRAMIN, 0x081C * 4) | 0x00080000); in NVLoadStateExt()
1157 NV_RD32(par->PRAMIN, 0x0820 * 4) | 0x00080000); in NVLoadStateExt()
1165 NV_RD32(par->PRAMIN, 0x0824 * 4) | 0x00020000); in NVLoadStateExt()
1167 NV_RD32(par->PRAMIN, in NVLoadStateExt()
1193 NV_RD32(par->PGRAPH, 0x0710) & 0x0007ff00); in NVLoadStateExt()
1195 NV_RD32(par->PGRAPH, 0x0710) | 0x00020100); in NVLoadStateExt()
1204 NV_RD32(&par->PFB[(0x0240 / 4) + i], in NVLoadStateExt()
1221 NV_RD32(par->PGRAPH, 0x0bc4) | in NVLoadStateExt()
1224 j = NV_RD32(par->REGS, 0x1540) & 0xff; in NVLoadStateExt()
1251 NV_RD32(par->PFB, 0x33C) & in NVLoadStateExt()
1266 NV_RD32(par->PFB, 0x020C)); in NVLoadStateExt()
1270 NV_RD32(par->PFB, 0x020C)); in NVLoadStateExt()
1274 NV_RD32(par->PRAMDAC, in NVLoadStateExt()
1287 NV_RD32(par->PRAMDAC, 0x0608) | in NVLoadStateExt()
1294 NV_RD32(par->PRAMDAC, 0x0608) | in NVLoadStateExt()
1362 NV_RD32(par->PFB, 0x0240 +i*4)); in NVLoadStateExt()
1364 NV_RD32(par->PFB, 0x0240 +i*4)); in NVLoadStateExt()
1375 NV_RD32(par->PFB, in NVLoadStateExt()
1379 NV_RD32(par->PFB, in NVLoadStateExt()
1386 NV_RD32(par->PFB, in NVLoadStateExt()
1396 NV_RD32(par->PFB, in NVLoadStateExt()
1405 NV_RD32(par->PFB, 0x0200)); in NVLoadStateExt()
1407 NV_RD32(par->PFB, 0x0204)); in NVLoadStateExt()
1409 NV_RD32(par->PFB, 0x0200)); in NVLoadStateExt()
1411 NV_RD32(par->PFB, 0x0204)); in NVLoadStateExt()
1425 NV_RD32(par->PFB, 0x0200)); in NVLoadStateExt()
1427 NV_RD32(par->PFB, 0x0204)); in NVLoadStateExt()
1430 NV_RD32(par->PFB, 0x0200)); in NVLoadStateExt()
1432 NV_RD32(par->PFB, 0x0204)); in NVLoadStateExt()
1435 NV_RD32(par->PFB, 0x0200)); in NVLoadStateExt()
1437 NV_RD32(par->PFB, 0x0204)); in NVLoadStateExt()
1448 NV_RD32(par->PFB, 0x0200)); in NVLoadStateExt()
1450 NV_RD32(par->PFB, 0x0204)); in NVLoadStateExt()
1453 NV_RD32(par->PFB, 0x0200)); in NVLoadStateExt()
1456 NV_RD32(par->PFB, 0x0204)); in NVLoadStateExt()
1521 NV_WR32(par->PRAMDAC, 0x0404, NV_RD32(par->PRAMDAC, 0x0404) | in NVLoadStateExt()
1643 state->vpll = NV_RD32(par->PRAMDAC0, 0x0508); in NVUnloadStateExt()
1645 state->vpll2 = NV_RD32(par->PRAMDAC0, 0x0520); in NVUnloadStateExt()
1647 state->vpllB = NV_RD32(par->PRAMDAC0, 0x0578); in NVUnloadStateExt()
1648 state->vpll2B = NV_RD32(par->PRAMDAC0, 0x057C); in NVUnloadStateExt()
1650 state->pllsel = NV_RD32(par->PRAMDAC0, 0x050C); in NVUnloadStateExt()
1651 state->general = NV_RD32(par->PRAMDAC, 0x0600); in NVUnloadStateExt()
1652 state->scale = NV_RD32(par->PRAMDAC, 0x0848); in NVUnloadStateExt()
1653 state->config = NV_RD32(par->PFB, 0x0200); in NVUnloadStateExt()
1656 state->control = NV_RD32(par->PRAMDAC0, 0x0580); in NVUnloadStateExt()
1660 state->head = NV_RD32(par->PCRTC0, 0x0860); in NVUnloadStateExt()
1661 state->head2 = NV_RD32(par->PCRTC0, 0x2860); in NVUnloadStateExt()
1667 state->cursorConfig = NV_RD32(par->PCRTC, 0x0810); in NVUnloadStateExt()
1670 state->dither = NV_RD32(par->PRAMDAC, 0x0528); in NVUnloadStateExt()
1672 state->dither = NV_RD32(par->PRAMDAC, 0x083C); in NVUnloadStateExt()