Lines Matching refs:PFB
391 cfg1 = NV_RD32(par->PFB, 0x00000204); in nv4UpdateArbitrationSettings()
630 cfg1 = NV_RD32(par->PFB, 0x0204); in nv10UpdateArbitrationSettings()
634 sim_data.memory_type = (NV_RD32(par->PFB, 0x0200) & 0x01) ? 1 : 0; in nv10UpdateArbitrationSettings()
932 state->config = NV_RD32(par->PFB, 0x00000200); in NVCalcStateExt()
960 NV_WR32(par->PFB, 0x0200, state->config); in NVLoadStateExt()
964 NV_WR32(par->PFB, 0x0240 + (i * 0x10), 0); in NVLoadStateExt()
965 NV_WR32(par->PFB, 0x0244 + (i * 0x10), in NVLoadStateExt()
978 NV_WR32(par->PFB, 0x0600 + (i * 0x10), 0); in NVLoadStateExt()
979 NV_WR32(par->PFB, 0x0604 + (i * 0x10), in NVLoadStateExt()
1204 NV_RD32(&par->PFB[(0x0240 / 4) + i], in NVLoadStateExt()
1250 NV_WR32(par->PFB, 0x033C, in NVLoadStateExt()
1251 NV_RD32(par->PFB, 0x33C) & in NVLoadStateExt()
1266 NV_RD32(par->PFB, 0x020C)); in NVLoadStateExt()
1270 NV_RD32(par->PFB, 0x020C)); in NVLoadStateExt()
1362 NV_RD32(par->PFB, 0x0240 +i*4)); in NVLoadStateExt()
1364 NV_RD32(par->PFB, 0x0240 +i*4)); in NVLoadStateExt()
1375 NV_RD32(par->PFB, in NVLoadStateExt()
1379 NV_RD32(par->PFB, in NVLoadStateExt()
1386 NV_RD32(par->PFB, in NVLoadStateExt()
1396 NV_RD32(par->PFB, in NVLoadStateExt()
1405 NV_RD32(par->PFB, 0x0200)); in NVLoadStateExt()
1407 NV_RD32(par->PFB, 0x0204)); in NVLoadStateExt()
1409 NV_RD32(par->PFB, 0x0200)); in NVLoadStateExt()
1411 NV_RD32(par->PFB, 0x0204)); in NVLoadStateExt()
1425 NV_RD32(par->PFB, 0x0200)); in NVLoadStateExt()
1427 NV_RD32(par->PFB, 0x0204)); in NVLoadStateExt()
1430 NV_RD32(par->PFB, 0x0200)); in NVLoadStateExt()
1432 NV_RD32(par->PFB, 0x0204)); in NVLoadStateExt()
1435 NV_RD32(par->PFB, 0x0200)); in NVLoadStateExt()
1437 NV_RD32(par->PFB, 0x0204)); in NVLoadStateExt()
1448 NV_RD32(par->PFB, 0x0200)); in NVLoadStateExt()
1450 NV_RD32(par->PFB, 0x0204)); in NVLoadStateExt()
1453 NV_RD32(par->PFB, 0x0200)); in NVLoadStateExt()
1456 NV_RD32(par->PFB, 0x0204)); in NVLoadStateExt()
1653 state->config = NV_RD32(par->PFB, 0x0200); in NVUnloadStateExt()