67 } dispc_compat;  variable
76 	spin_lock_irqsave(&dispc_compat.irq_stats_lock, flags);  in dispc_dump_irqs()
78 	stats = dispc_compat.irq_stats;  in dispc_dump_irqs()
79 	memset(&dispc_compat.irq_stats, 0, sizeof(dispc_compat.irq_stats));  in dispc_dump_irqs()
80 	dispc_compat.irq_stats.last_reset = jiffies;  in dispc_dump_irqs()
82 	spin_unlock_irqrestore(&dispc_compat.irq_stats_lock, flags);  in dispc_dump_irqs()
135 	mask = dispc_compat.irq_error_mask;  in _omap_dispc_set_irqs()
138 		isr_data = &dispc_compat.registered_isr[i];  in _omap_dispc_set_irqs()
159 	spin_lock_irqsave(&dispc_compat.irq_lock, flags);  in omap_dispc_register_isr()
163 		isr_data = &dispc_compat.registered_isr[i];  in omap_dispc_register_isr()
175 		isr_data = &dispc_compat.registered_isr[i];  in omap_dispc_register_isr()
193 	spin_unlock_irqrestore(&dispc_compat.irq_lock, flags);  in omap_dispc_register_isr()
197 	spin_unlock_irqrestore(&dispc_compat.irq_lock, flags);  in omap_dispc_register_isr()
210 	spin_lock_irqsave(&dispc_compat.irq_lock, flags);  in omap_dispc_unregister_isr()
213 		isr_data = &dispc_compat.registered_isr[i];  in omap_dispc_unregister_isr()
231 	spin_unlock_irqrestore(&dispc_compat.irq_lock, flags);  in omap_dispc_unregister_isr()
239 	if ((status & dispc_compat.irq_error_mask) == 0)  in print_irq_status()
271 	spin_lock(&dispc_compat.irq_lock);  in omap_dispc_irq_handler()
278 		spin_unlock(&dispc_compat.irq_lock);  in omap_dispc_irq_handler()
283 	spin_lock(&dispc_compat.irq_stats_lock);  in omap_dispc_irq_handler()
284 	dispc_compat.irq_stats.irq_count++;  in omap_dispc_irq_handler()
285 	dss_collect_irq_stats(irqstatus, dispc_compat.irq_stats.irqs);  in omap_dispc_irq_handler()
286 	spin_unlock(&dispc_compat.irq_stats_lock);  in omap_dispc_irq_handler()
299 	memcpy(registered_isr, dispc_compat.registered_isr,  in omap_dispc_irq_handler()
302 	spin_unlock(&dispc_compat.irq_lock);  in omap_dispc_irq_handler()
316 	spin_lock(&dispc_compat.irq_lock);  in omap_dispc_irq_handler()
318 	unhandled_errors = irqstatus & ~handledirqs & dispc_compat.irq_error_mask;  in omap_dispc_irq_handler()
321 		dispc_compat.error_irqs |= unhandled_errors;  in omap_dispc_irq_handler()
323 		dispc_compat.irq_error_mask &= ~unhandled_errors;  in omap_dispc_irq_handler()
326 		schedule_work(&dispc_compat.error_work);  in omap_dispc_irq_handler()
329 	spin_unlock(&dispc_compat.irq_lock);  in omap_dispc_irq_handler()
346 	spin_lock_irqsave(&dispc_compat.irq_lock, flags);  in dispc_error_worker()
347 	errors = dispc_compat.error_irqs;  in dispc_error_worker()
348 	dispc_compat.error_irqs = 0;  in dispc_error_worker()
349 	spin_unlock_irqrestore(&dispc_compat.irq_lock, flags);  in dispc_error_worker()
407 	spin_lock_irqsave(&dispc_compat.irq_lock, flags);  in dispc_error_worker()
408 	dispc_compat.irq_error_mask |= errors;  in dispc_error_worker()
410 	spin_unlock_irqrestore(&dispc_compat.irq_lock, flags);  in dispc_error_worker()
420 	spin_lock_init(&dispc_compat.irq_stats_lock);  in dss_dispc_initialize_irq()
421 	dispc_compat.irq_stats.last_reset = jiffies;  in dss_dispc_initialize_irq()
425 	spin_lock_init(&dispc_compat.irq_lock);  in dss_dispc_initialize_irq()
427 	memset(dispc_compat.registered_isr, 0,  in dss_dispc_initialize_irq()
428 			sizeof(dispc_compat.registered_isr));  in dss_dispc_initialize_irq()
430 	dispc_compat.irq_error_mask = DISPC_IRQ_MASK_ERROR;  in dss_dispc_initialize_irq()
432 		dispc_compat.irq_error_mask |= DISPC_IRQ_SYNC_LOST2;  in dss_dispc_initialize_irq()
434 		dispc_compat.irq_error_mask |= DISPC_IRQ_SYNC_LOST3;  in dss_dispc_initialize_irq()
436 		dispc_compat.irq_error_mask |= DISPC_IRQ_VID3_FIFO_UNDERFLOW;  in dss_dispc_initialize_irq()
444 	INIT_WORK(&dispc_compat.error_work, dispc_error_worker);  in dss_dispc_initialize_irq()
448 	r = dispc_request_irq(omap_dispc_irq_handler, &dispc_compat);  in dss_dispc_initialize_irq()
459 	dispc_free_irq(&dispc_compat);  in dss_dispc_uninitialize_irq()